Floating point binary quad word format multiply instruction unit

Details Floating point binary quad word format multiply instruction unit Floating point binary quad word format multiply instruction unit

1998-03-04

2000-04-25

Ngo, Ohuong Dinh

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

G06F 738

Patent

active

060555548

ABSTRACT:
An IEEE 754 standard floating point multiply instruction for binary extended precision format can be executed with a quad word format on an S/390 process. The multiplication calculation multiplies each partition by each other. In the multiplication calculation process dataflow process of either operand is a denormalized number, they are normalized at a stage which creates an expanded exponent range of one more bit, and the calculation continues to a parallel path multiplexor stage, but if neither operand is denormalized then the exponent of the number is expended and the calculation splits into four parallel paths, wherein two operand's sign bits are processed in a sign calculation block stage, the operands' two 16 bit binary exponents are processed by an exponent conversion block stage, and a partition multiplicand significand block stage receives a 113 bit multiplicand significand input for a fourth path. In this calculation third and fourth paths converge with a calculation which provides partial products and intermediate sums and finally a final product as a calculation block stage output, and this output and the exponent from said second path and the sign bit from said first path merge to provide a product which is represented in hexadecimal internal format and is converted back to binary format in calculation block stage and rounded.

REFERENCES:
patent: 4594679 (1986-06-01), George et al.
patent: 5687106 (1997-11-01), Schwarz et al.
patent: 5740093 (1998-04-01), Sharangpani
patent: 5909385 (1999-06-01), Nishiyama et al.
"CMOS Floating-Point Unit For The S/390 Parallel Enterprise Server G4" by Schwarz et al., IBM Journal of Research and Development, vol. 41, No. 4/5, Jul./Sep. 1997, pp. 475-488.
"Hardware Implementation of Sine/Cosine Polynomial Approximation" by Desrosiers et al., IBM TDB, vol. 37, No. 11, Nov. 1994, pp. 609-613.

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