Floating point arithmetic unit with size efficient pipelined mul

Details Floating point arithmetic unit with size efficient pipelined mul Floating point arithmetic unit with size efficient pipelined mul

1991-12-16

1993-08-31

Nguyen, Long T.

Boots, shoes, and leggings

G06F 738

Patent

active

052414930

ABSTRACT:
An architecture and method relating to a floating point operation which performs the mathematical computation of A*B+C. The multiplication is accomplished in two or more stages, each stage involving corresponding sets of partial products and concurrently accomplished incremental summations. A pipelined architecture provides for the summation of the least significant bits of an intermediate product with operand C at a stage preceding entry into a full adder. Thereby, a significant portion of the full adder can be replaced by a simpler and smaller incrementer circuit. Partitioning of the multiplication operation into two or more partial product operations proportionally reduces the size of the multiplier required. Pipelining and concurrence execution of multiplication and addition operation in the multiplier provides in two cycles the results of the mathematical operation A*B+C while using a full adder of three-quarters normal size.

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IBM Technical Disclosure Bulletin vol. 30 No. 3 Aug. 1987 "Multiply-Addition-An Ultra High Performance Dataflow", pp. 982-987.
"Computer Architecture A Quantitative Approach"-David A. Patterson, John L. Hennessy, 1990, pp. A-42 to A-49.

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