Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
1998-12-22
2001-11-06
Mai, Tan V. (Department: 2121)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Reexamination Certificate
active
06314442
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a floating-point arithmetic unit for performing arithmetic operations of floating-point data, and particularly to nearest value round-off according to IEEE Std 754 referred to as business standard.
2. Description of the Background Art
IEEE Std 754 is practically a business standard about the floating-point arithmetic operations, whose outstanding characteristics include the following four round-off modes:
(1) Nearest value round-off;
(2) + Infinity round-off;
(3) − Infinity round-off; and
(4) Round-down.
When a floating-point arithmetic unit is configured with hardware to perform the above-mentioned round-off modes (1) to (4), the circuit configuration of the floating-point arithmetic unit will be complicated, leading to an increase in throughput.
FIG. 15
shows a part relating to round-off processing in such a floating-point arithmetic unit as is disclosed in Japanese Patent Laying-Open No.6-59858 as an example. The mantissa adder-subtracter portion MAP performs addition or subtraction of mantissa data A and B in two pieces of floating-point data. It is assumed here that the preceding and following processing system is configured so that the result of addition or subtraction is always presented as an absolute value, or a positive value. The ISB determination portion BJP determines whether the high-order three bits in the arithmetic result D made by the mantissa adder-subtracter portion MAP are “0” or not. The increment signal generating portion IP generates an increment signal for indicating a bit to be rounded up (an increment bit position) by using the determination result from the LSB determination portion BJP. The incrementer IMa applies increment to the bit indicated by the increment signal among the bits forming the arithmetic result D. The round-off decision portion RJPa decides whether to round by using the determination result from the LSB determination portion BJP. When the decision result from the round-off decision portion RJPa indicates round-off, the selector S
1
selects and outputs the arithmetic result from the incrementer IMa. In other cases, it selects and outputs the arithmetic result D from the mantissa adder-subtracter portion MAP. The character MO indicates the output result from the selector S
1
.
However, in the arithmetic result made by the mantissa adder-subtracter portion MAP, the values are sequentially determined from the least significant bit side to the most significant bit side by carries occurring in this direction when adding the mantissa data A and B, for example. Accordingly, the increment signal generating portion IP has to wait until all bits in the arithmetic result D have been determined to specify the increment bit position. This waiting time increases the throughput.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention, a floating-point arithmetic unit comprises: an arithmetic operation portion receiving mantissa data in first floating-point data and mantissa data in second floating-point data, for performing arithmetic operation of the data; an increment portion connected to the arithmetic operation portion, receiving the arithmetic result made by the arithmetic operation portion, for applying increment to a bit in the arithmetic result which corresponds to the LSB on the assumption that either no overflow shift of the MSB in the arithmetic result or any cancellation shift of the MSB in the arithmetic result occurs; a round-off decision portion receiving the arithmetic result made by the arithmetic operation portion, for deciding whether to round up a bit in a position one place lower than the LSB on the basis of the arithmetic result; and a first selector receiving the arithmetic result made by the arithmetic operation portion, the arithmetic result made by the increment portion, and the decision result made by the round-off decision portion, for selectively outputting one of the arithmetic result from the increment portion and the arithmetic result from the arithmetic operation portion in accordance with the decision result from the round-off decision portion.
Preferably, according to a second aspect, in the floating-point arithmetic unit, the increment portion comprises an LSB specify portion for determining whether the arithmetic operation is an effective addition or an effective subtraction and specifying the LSB in accordance with the result of the determination.
Preferably, according to a third aspect, in the floating-point arithmetic unit, the LSB specify portion comprises an increment bit determination portion for making the determination, and a second selector receiving the determination result made by the increment bit determination portion, for selectively outputting one of predetermined data for effective addition and predetermined data for effective subtraction in accordance with the determination result made by the increment bit determination portion, and the increment portion further comprises an incrementer receiving the arithmetic result from the arithmetic operation portion and the selected result made by the second selector, for adding these results to perform the increment.
Preferably, according to a fourth aspect, in the floating-point arithmetic unit, the LSB specify portion comprises an increment bit determination portion for making the determination and selectively outputting data for effective addition or data for effective subtraction in accordance with the result of the determination, and the increment portion further comprises an incrementer receiving the arithmetic result made by the arithmetic operation portion and an output from the increment bit determination portion, for adding them to perform the increment.
Preferably, according to a fifth aspect, in the floating-point arithmetic unit, the LSB specify portion comprises an increment bit determination portion for making the determination, and a bit shifter receiving the arithmetic result made by the arithmetic operation portion and the determination result made by the increment bit determination portion, for shifting the arithmetic result made by the arithmetic operation portion in accordance with the determination result made by the increment bit determination portion, and the increment portion further comprises an incrementer receiving the arithmetic result made by the arithmetic operation portion outputted through the bit shifter, for performing the increment.
Preferably, according to a sixth aspect, in the floating-point arithmetic operation unit, the LSB specify portion comprises an increment bit determination portion for making the determination, a first bit shifter receiving the mantissa data in the first floating-point data and the determination result made by the increment bit determination portion, for shifting the mantissa data in the first floating-point data in accordance with the determination result made by the increment bit determination portion and outputting the shifted data to the arithmetic operation portion, and a second bit shifter receiving the mantissa data in the second floating-point data and the determination result made by the increment bit determination portion, for shifting the mantissa data in the second floating-point data in accordance with the determination result made by the increment bit determination portion and outputting the shifted data to the arithmetic operation portion, and wherein the increment portion further comprises an incrementer receiving the arithmetic result made by the arithmetic operation portion, for performing the increment.
Preferably, according to a seventh aspect, in the floating-point arithmetic unit, the data for effective addition selectively outputted from the increment bit determination portion is “1”, and the data for effective subtraction selectively outputted from the increment bit determination portion is “0”, and the incrementer comprises a full adder receiving the least significant bit in the arithmetic result made by the arithmetic operation portion, the outp
Mai Tan V.
Mitsubishi Denki & Kabushiki Kaisha
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
LandOfFree
Floating-point arithmetic unit which specifies a least... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Floating-point arithmetic unit which specifies a least..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Floating-point arithmetic unit which specifies a least... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2615644