Floating point arithmetic unit having logic for quad precision a

Details Floating point arithmetic unit having logic for quad precision a Floating point arithmetic unit having logic for quad precision a

1994-10-27

1997-05-20

Ngo, Chuong D.

Boots, shoes, and leggings

36471503, G06F 700, G06F 738

Patent

active

056318596

ABSTRACT:
A floating point processing system which uses a multiplier unit and an adder unit to perform properly rounded quad precision floating point arithmetic operations using double-extended hardware. The floating point processing system includes quad data muxes for converting a quantity between a quad precision representation and a two double-extended precision quantities and vice versa, wherein the sum, if added at infinite precision, of the two double-extended precision quantities is equal to the quad precision quantity. The floating point processing system further include hardware for performing arithmetic operations on double-extended precision quantities.

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Karp, A., "Speeding up N-body Calculations on Machines without Hardware Square Root", Document No. G320-3565, IBM Scientific Center, pp. 1-7 Apr. 1992.
Markstein, P. W., "Computation of Elementary Functiuons of the IBM RISC System/6000 Processor", IBM Journal of Research and Development, vol. 34, No. 1, Jan. 1990, pp. 111-119.

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