Floating-point arithmetic processing apparatus

Details Floating-point arithmetic processing apparatus Floating-point arithmetic processing apparatus

1997-01-29

1999-08-03

Kizou, Hassan

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

708205, G06F 752

Patent

active

059318953

ABSTRACT:
A floating-point arithmetic processing apparatus has a circuit for generating a limit value for normalization shift by subtracting an exponent of the minimum value of a normalized number from a value of an exponent of an intermediate result, and a circuit for generating, as a normalization shift number, smaller one of a shift number necessary for making the mantissa of the intermediate result a normalized number and the limit value for normalization shift. The floating-point arithmetic processing apparatus further has a circuit having a circuit for detecting a condition for overflow before the rounding process and a circuit for generating a value in the case of overflow, so that a predetermined value is delivered as a final result only when the overflow condition is detected before the rounding process but in the other case, a result obtained by performing the normalization process and the rounding process is delivered. When no overflow takes place before the rounding process but overflow occurs after the rounding process, the result obtained by performing the normalization process and the rounding process is delivered as a final result.

REFERENCES:
patent: 4779220 (1988-10-01), Nukiyama
patent: 5289396 (1994-02-01), Taniguchi
patent: 5469377 (1995-11-01), Amano
patent: 5487022 (1996-01-01), Simpson et al.
American National Standards Institute, Binary Floating-point Arithmetic, ANSI/IEEE Std 754-1985, Jul. 26, 1985.

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