Floating point arithmetic logic unit rounding using at least...

Details Floating point arithmetic logic unit rounding using at least... Floating point arithmetic logic unit rounding using at least...

1998-09-18

2001-03-06

Ngo, Ohuong Dinh (Department: 2121)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S498000

Reexamination Certificate

active

06199089

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to performing digital data processing and in particular to digital data processing using a floating point unit in an arithmetic logic unit.
BACKGROUND
As is well-known in the art, arithmetic logic units often perform data processing in a floating point format. Floating point units can be used to perform high precision arithmetic calculations on real, integer, and BCD integers. Moreover, floating point units can be used to perform conversion of numbers between floating point and integer formats.
According to IEEE standard 754, floating point numbers are divided into three sections or fields: a sign field, an exponent field, and a significand or mantissa field. Each field has a finite number of bits, e.g., a mantissa field in an extended precision format has 64 bits. During arithmetic operations that produce a result with a number of bits greater than the number of bits in the field, it is necessary to round the result to fit within the field.
Conventionally, in a floating point unit addition and subtraction operations are performed serially with the rounding operation. Typically, the mantissa of the operands are first normalized, a carry propagate add derives an unrounded result, and a rounding unit inspects the unrounded result and other bits, such as the sticky bit and rounding bit, to determine if it is necessary to round up or round down to obtain the final result. The unrounded result from the carry propagate adder is then incremented if the rounding unit indicates that is necessary. Each of the operations performed by the floating point unit to obtain the final result requires a finite amount of time. Because the steps are performed serially, the process is slow. Moreover, the use of a carry propagate adder is costly because it requires a large amount of area on the chip.
Thus, there is need for a floating point unit that performs arithmetic operations, such as addition and subtraction, in a non-serial manner to obtain a final result in an efficient manner. Further, there is a need for a floating point unit that performs arithmetic operations while avoiding the use of a carry propagate adder.
SUMMARY
A floating point unit includes an adding unit, such as a half adding unit, that generates a sum of a first mantissa and a second mantissa. Where a half adding unit is used a carry is generated along with the sum. At least one least significant bit from the sum and the carry is separated and received by a rounding unit. Where an addition operation is being performed, two least significant bits from the sum and the carry are removed and received by the rounding unit. The rounding unit uses the least significant bits of the sum and carry, along with a sticky bit, rounding bit and the predicted sign of the result to generate a carry in bit and rounded at least one least significant bit.
In a parallel path, the sum and carry are each formatted if a subtraction operation is being performed, and the result of the sum and carry is tested to see if an overflow condition exists. The sum and carry are then summed in an additional adding unit to produce an unincremented sum and an incremented sum, which are placed in a multiplexer. The carry in bit is used to select one of the unincremented sum and incremented sum. The rounded at least one least significant bit is then united with the selected unincremented sum or incremented sum.
By using parallel paths for these operations it is possible to test for overflow and format the sum and carry for subtraction while concurrently determining the rounding of the result. Consequently, an arithmetic operation may be performed without unduly slowing the processing of the result.


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