Floating point arithmetic logic unit leading zero count...

Details Floating point arithmetic logic unit leading zero count... Floating point arithmetic logic unit leading zero count...

1998-09-18

2001-03-20

Ngo, Ohuong Dinh (Department: 2121)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S211000

Reexamination Certificate

active

06205461

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to performing digital data processing and in particular to digital data processing using a floating point unit in an arithmetic logic unit.
BACKGROUND
As is well-known in the art, arithmetic logic units often perform data processing in a floating point format. Floating point units can be used to perform high precision arithmetic calculations on real, integer, and BCD integers. Moreover, floating point units can be used to perform conversion of numbers between floating point and integer formats.
According to IEEE standard 754, floating point numbers are divided into three sections or fields: a sign field, an exponent field, and a fraction or mantissa field. Floating point numbers are typically represented in a normalized form, i.e., except for zero, the mantissa is made up of an integer 1 followed by a fraction (1.ffff . . . f) where the integer 1 is implied. Normalization maximizes the number of significant digits that can be represented within a mantissa of a given length.
Often floating point architecture includes shifting units to normalize a result. Typically the shifting units are controlled by a counting unit, which is used to count a number of leading zeros in a preliminary result. Using the information obtained in the counting unit, the shifting unit can then appropriately shift the bits of data to normalize the result, where for each shift of the result to the left, the exponent is decremented by one. However, counting the leading zeros to normalize the result takes time, which consequently, delays obtaining the normalized result.
Thus, there is a need for a floating point unit that allows for normalizing the result without causing a delay in obtaining the result.
SUMMARY
A floating point arithmetic logic unit includes a carry propagate adder to generate an incremented and unincremented result. An inverter may be used to generate a complemented result. Two select units, each coupled to the carry propagate adder and inverter, store the incremented, unincremented and complemented result. A fast rounding unit coupled to one of the select units selects one of the results as an approximation based on the equality or inequality of the exponents of the operands, the relative sizes of the mantissas of the operands, and the presence of a guard bit. The select unit that is coupled to the fast rounding unit is also coupled to a leading zero count unit, which receives the result selected by the fast rounding unit. A slower rounding unit coupled to the other select units is used to make an accurate selection of one of the results based on the rounding mode used, whether the result is exact or inexact, and the sign of the result. Because the fast rounding unit quickly selects an approximate result, the leading zeros of the approximate result are counted while the slow rounding unit is selecting the most accurate result. The select unit that is coupled to the slow rounding unit is also connected to a shifting unit. Once the most accurate result is selected by the slow rounding unit, the bits can be left shifted in the shifting unit by an amount based on the leading zeros counted in the approximate result. Thus, by counting the leading zeros in an approximate result, a normalized result can be quickly produced while avoiding delays caused by counting the leading zeros in the accurate result.


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