Floating-point arithmetic device

Details Floating-point arithmetic device Floating-point arithmetic device

2000-03-31

2003-05-27

Ngo, Chuong Dinh (Department: 2124)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S205000, C708S497000

Reexamination Certificate

active

06571264

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to floating-point arithmetic devices, and more particularly to a floating-point arithmetic device using a leading-zero anticipation circuit to increase an operation speed.
2. Description of the Prior Art
In a floating-point arithmetic device, generally, an input operand for calculation is composed of a sign block representing addition (“+”) or subtraction (“−”), an exponent block representing a magnitude of the operand and a significand block representing significant digits. For example, if the input operand is 0.11×2
8
, the exponent is “8” and the significand is “11”.
In floating-point addition, exponents of two significands are compared with each other and one of the significands wish the smaller exponent is shifted to the right. Then, the two significands are summed and the number of consecutive leading zeros is calculated from the summed result. This procedure is performed on the assumption that a most significant bit of the significand is always 1 for the effective use of hardware in the expression of a real number, which is called normalization.
The significand after this procedure of normalization is expressed in a range between 0.5 and 1.0.
Such a conventional floating-point arithmetic device will hereinafter be mentioned with reference to the accompanying drawings.
FIG. 1
is a block diagram showing the construction of a conventional TFT-LCD floating-point arithmetic device and
FIG. 2
is a detailed circuit diagram of a leading-zero anticipation circuit in FIG.
1
.
With reference to
FIG. 1
, the floating-point arithmetic device comprises an input aligner
2
for suitably aligning two input operands, a controller
1
for comparing exponents of the input operands aligned by the input aligner
2
with each other and generating a control signal in accordance with the compared result, and a first multiplexer
3
for selecting a larger one of the exponents of the input operands in response to the control signal from the controller
1
. A second multiplexer
4
selects a significand of one of the input operands with the larger exponent in response to the control signal from the controller
1
and a third multiplexer
5
selects a significand of the other input operand with a smaller one of the exponents in response to the control signal from the controller
1
. An exponent difference calculator
6
is adapted to calculate a difference between the exponents of the input operands. A right shifter
7
shifts the significand selected by the third multiplexer
5
to the right by the exponent difference calculated by the exponent difference calculator
6
to establish digit matching. A significand comparator
8
acts to compare the significands selected by the second and third multiplexers
4
and
5
with each other. First and second bit inverters
9
and
10
invert the significand selected by the second multiplexer
4
and the significand shifted by the right shifter
7
in response to an output signal from the significand comparator
8
, respectively, to take two's complements thereof for subtraction by an adder
11
which will hereinafter be mentioned. The adder
11
is adapted to add output values from the first and second bit inverters
9
and
10
. A leading-zero anticipation circuit
12
functions to anticipate the consecutiveness of leading zeros from the output values from the first and second bit inverters
9
and
10
. A leading-zero counter
13
counts the number of the leading zeros anticipated by the leading-zero anticipation circuit
12
. A rounding controller
14
is adapted to estimate a rounding condition to store an output value from the adder
11
in a specific bits number. As incrementer
17
adds “1” to a least significant bit of the stored value under the control of the rounding controller
14
. A left shifter
15
acts to shift the output value from the adder
11
to the left by the number counted by the leading-zero counter
13
. A selector
18
functions to select one of an output value from the left shifter
15
and an output value from the incrementer
17
under the control of the rounding controller
14
according to whether the right shifter
7
and second bit inverter
10
are in operation. A compensation shifter
19
shifts an output significand from the selector
18
to perform digit compensation when it is the maximum. An exponent subtracter
16
is adapted to subtract the number counted by the leading-zero counter
13
from the larger exponent selected by the first multiplexer
3
. A sign controller
20
determines a sign of the final output value according to signs of the input operands. An exponent incrementer
22
acts to increment an output exponent from the exponent subtracter
16
to compensate for the leading-bit position. An output aligner
21
is adapted to align an output sign from the sign controller
20
, an output exponent from the exponent incrementer
22
and an output significand from the compensation shifter
19
to provide the final output value.
The leading-zero anticipation circuit
12
has a construction as shown in FIG.
2
.
In
FIG. 2
, the leading-zero anticipation circuit
12
is shown to calculate bit values at respective digits of the significands of the two input operands, on the assumption that the significands are each composed of m bits A
m
, A
m−1
, . . . , A
i
, A
i−1
, . . . , A
1
, A
0
and B
m
, B
m−1
, . . . , B
i
, B
i−1
, . . . , B
1
, B
0
,. Namely, the leading-zero anticipation circuit
12
includes a NAND gate
23
for NANDing values of two input bits A, and B of the same digit, a NOR gate
24
for NORing the values of the two input bits A
i
and B
i
of the same digit, an inverter
25
for inverting an output value from the NOR gate
24
, an OR gate
26
for ORing the inverted ones of output values from the inverter
25
and NAND gate
23
, and a NAND gate
27
for NANDing the inverted one of the NORed result of values of two input bits A
i−1
and B
i−1
of the next digit and an output value from the OR gate
26
.
Now, the operation of the conventional floating-point arithmetic device with the above-mentioned construction will be described.
First inputted over respective external data buses are two operands, each of which is composed of a sign block representing addition (“+”) or subtraction (“−”), an exponent block representing a magnitude of the operand and a significand block representing significant digits.
The input aligner
2
suitably aligns the two input operands and the controller
1
compares exponents of the input operands aligned by the input aligner
2
with each other and generates a control signal in accordance with the compared result so that a significand of one of the input operands with the smaller exponent can be outputted through the third multiplexer
5
and the larger exponent can be outputted through the first multiplexer
3
.
As a result, in response to the control signal from the controller
1
, the first multiplexer
3
selects the larger exponent, the third multiplexer
5
selects the significand of the input operand with the smaller exponent and the second multiplexer
4
selects a significand of the other input operand with the larger exponent.
The exponent difference calculator
6
calculates a difference between the exponents of the input operands and the right shifter
7
shifts the significand selected by the third multiplexer
5
to the right by the exponent difference calculated by the exponent difference calculator
6
to establish digit matching.
The significand comparator
8
compares the significands selected by the second and third multiplexers
4
and
5
with each other.
In order to provide two's complements to input terminals of the adder
11
for subtraction, the first bit inverter
9
inverts the significand selected by the second multiplexer
4
in response to an output signal from the significand comparator
8
and the second bit inverter
10
inverts the significand shifted by the ri

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