Floating-point arithmetic apparatus

Details Floating-point arithmetic apparatus Floating-point arithmetic apparatus

1987-12-28

1990-01-23

Harkcom, Gary V.

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G06F 738

Patent

active

048962864

ABSTRACT:
A floating-point arithmetic apparatus includes a first device for matching scales of first and second floating-point data. A second device serves to perform addition and subtraction between outputs from the first device. A third device serves to normalize output from the addition/subtraction device. A fourth device serves to round off output from the third device. A fifth device serves to calculate an absolute value of output from the third device. The fourth device and the fifth device may include a common adder.

REFERENCES:
patent: 4488252 (1984-12-01), Vassar
patent: 4562553 (1985-12-01), Mattedi et al.
patent: 4644490 (1987-02-01), Kobayashi et al.
patent: 4698771 (1987-10-01), Mills et al.
"An American National Standard; IEEE Standard for Binary Floating-Point Arithmetic" sponsored by Standards Committee of the IEEE Computer Society; approved by IEEE Standards Board & American National Standards Institute; ANSI/IEEE Std. 754--1985.

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