Floating-point and fixed-point addition-subtraction assembly

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364768, G06F 738

Patent

active

053696077

ABSTRACT:
Apparatus for use in a floating-point and fixed-point adder-subtractor assembly. The apparatus includes a comparator and selector circuit disposed prior to an adder-subtracter for determining a larger and smaller operand prior to the addition and subtraction operation. The comparator and selector circuit inputs the larger operand into a first predetermined input of the adder-subtracter and the smaller operand into a second predetermined input of the adder-subtracter. Additionally, first and second selector circuits may be provided for multiplexing first and second fixed point data operands into the first and second inputs of the adder-subtracter, respectively. A shifter is provided for shifting at least one of the operands prior to inputting the operand into the adder-subtracter for selectively performing a position alignment. Accordingly, a simplified structure provides fixed-point and floating-point data addition-subtraction in a highly efficient manner.

REFERENCES:
patent: 4511990 (1985-04-01), Hagiwara et al.
patent: 4620292 (1986-10-01), Hagiwara et al.
patent: 4999803 (1991-03-01), Turrini et al.
patent: 5136536 (1992-08-01), Ng
patent: 5146419 (1992-09-01), Miyoshi et al.
patent: 5222037 (1993-06-01), Taniguchi

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