Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2000-03-09
2003-05-27
Ngo, Chuong Dinh (Department: 2124)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Reexamination Certificate
active
06571267
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a floating point execution unit having a canceling prediction circuit and a prediction error detection circuit for judging the necessary of the shifting for the compensation of one bit error, and more particularly, the invention relates to a method to perform the arithmetic operation at high speed.
2. Description of the Related Art
In order to true up or justify leftward the most significant bit of a mantissa part onto a particular position or digit, a normalization process is needed in a floating point execution unit after the calculation operation of addition and subtraction has been completed. This normalization process is such a process that the number of “0's” or “1's” which are aligned continuously from the most significant digits of the arithmetic result are counted and then the arithmetic result is shifted leftward by digits corresponding to the counted number of leading “0's” or “1's”.
With the progress of the processor speed, such a method has been proposed that enables to predict the number of “0's” or “1's” which are aligned continuously from the most significant digits of the arithmetic result in parallel with the calculation process (LZA: Leading Zero Anticipation method, a canceling prediction method or a canceling prediction circuit). This canceling prediction method has been set forth in papers published by E. HOKENEK (IBM, J. RES. DEVELP. VOL.34, 1990, pp.71-77), H. SUZUKI et al.(CICC Cproc., 1995, pp.27.5.1-27.5.4), etc.
The basic conception of the canceling prediction method of E. HOKENEK briefly will be explained below.
First, corresponding bits in mantissa parts of two operands are compared. Second, three inputs G, Z, and P are defined based on the comparison result of each comparison operation. The G-inputs indicates that corresponding bits are both “1”. The Z-inputs indicates that corresponding bits are both “0”. The P-inputs indicates that corresponding bits are “1” and “0”. Because each comparison result has one of the G-inputs, Z-inputs, and P-inputs, the canceling bit at which canceling occurs can be specified when the comparison results of the corresponding bits of the mantissa parts are detected from the most significant bit to the least significant bit according to the state transition diagram shown in FIG.
1
.
For example, the following subtraction will be considered:
1.00010000000000010000000
=Fa<
23
:
0
>−)
1.00001111000000000000000
=Fb<
23
:
0
>
0.00000001000000010000000
An actual operation for the above subtraction performs an addition between Fa<
23
:
0
> and a complement on Fb<
23
:
0
> are added. The complement on Fb<
23
:
0
> is obtained by adding the least significant bit A
1
″ to Fbx<
23
:
0
> obtained by inverting Fb<
23
:
0
>.
That is to say,
1.00010000000000010000000
=Fa<
23
:
0
>+)
0.11110000111111111111111
=Fbx<
23
:
0
>
0.00000001000000001111111
In addition,
0.00000001000000001111111+) 1
0.00000001000000010000000
The result of this arithmetic operation has the canceling of 8 bits. In general, the canceling prediction in order to predict the canceling is performed with subtraction operation in parallel.
Firstly, when each bit in the result of the arithmetic operation described above is defined with the three inputs, G (both “1”), Z (both “0”), and P (“1” and “0”), the following result is obtained.
1.00010000000000010000000
=Fa<
23
:
0
>+)
0.1111000011111111111111
=Fbx<
23
:
0
>
P.PPPGZZZZPPPPPPPGPPPPPPP
0.00000001000000010000000
=EE<
23:0>
When the above result (P.PPPGZZZZPPPPPPPGPPPPPPP) is checked from the most significant bit to the least significant bit based on the state transition diagram shown in
FIG. 1
, the P state is repeated in the pattern “P.PPP”,the following inputs pattern “G” transits from the P state to the G state. Then, the Z state is repeated in the pattern “ZZZZ”. The canceling is detected at the following P state.
In the paper of H. SUZUKI, only signals (canceling prediction bit signals) are extracted. These signals are so predicted that the: canceling from the Z state shown in
FIG. 1
occurs. Then, a priority encoder detects the most significant bit in these signals.
This operation realizes the logic to generate the canceling prediction bit signal based on that the difference of mantissa parts in two operands have already been known. Because the two operands are switched in order to obtain the positive result of, subtraction when subtraction is performed, there is no transition to the G state.
That is, canceling occurs only when the symbol pattern in the alignment of the result changes from the Z-inputs to the P-inputs (Z→P) or the G-inputs (Z→G). This meaning is defined by using the following logic:
EE<i>
=(
Z<i
> and
G<i−
1>) or (
Z<i
> and
P<i−
1>).
Thus, the canceling bit prediction signal EE<i> can be generated by checking adjacent 2 bits in the result of the arithmetic operation. The above example of subtraction shows EE<
15
>=“1” at which the canceling occurs. In order to convert the position of the canceling to a binary number, a priority encoder is used because the most significant bit of the value “1” in the EE<i> has a significant meaning. By passing the EE<i> through the priority encoder, the position at which the canceling occurs can be thereby represented by the binary number.
In these method described above, the canceling position is detected from the most significant bit of the result toward the least significant bit. However, the position of the canceling is changed by a carry signal propagated from a lower significant bit. In the above example, a carry signal is propagated from the bit number <
7
>. If the carry propagation does not occur, the position of the canceling is shifted rightward by one bit. That is, the canceling prediction by the above two methods includes one bit prediction error.
By the way, the normalization process performs a left shifting operation based on the result obtained by the canceling prediction circuit. However, because the result of the canceling prediction circuit includes an one bit prediction error, it must be necessary to perform the shift operation for the one bit error compensation immediately after the left shifting process for the normalization.
The one bit prediction error can be detected by checking the most significant bit in the arithmetic result that has been normalized. By using the detection result, it may be judged whether the compensation operation for one bit error is necessary or not.
The Japanese Laid open publication number JP-A-10/6026 proposed and disclosed a method to detect the one bit prediction error with the canceling prediction operation, simultaneously.
Next, a description will be given of the configuration of conventional floating point execution units.
FIG. 2
shows an example of a conventional typical floating point execution unit including a conventional canceling prediction circuit (a leading zero anticipator).
In the conventional floating point execution unit shown in
FIG. 2
, a comparison of exponent parts is executed before addition and subtraction, and then a mantissa part of the operand having the smaller exponent part based on the comparison result is shifted to the right direction (alignment). In addition to this operation, the normalization (left shifting) is performed after subtraction (or addition).
In the conventional floating point execution unit having the above configuration, the canceling prediction circuit performs the canceling prediction by using two operands after the alignment of the mantissa parts before addition and subtraction.
The comparison circuit
1
performs the comparison of the difference of exponent parts in the operands. The pair of selectors
2
and
3
inverts one of the mantissa parts Fa<
23
:
0
> and Fb<
23
:
0
>
Do Chat C
Ngo Chuong Dinh
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