Floating point addition methods and apparatus

Boots – shoes – and leggings

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

36474803, G06F 742, G06F 738

Patent

active

058089268

ABSTRACT:
A floating point addition unit includes two subunits each of which performs the addition. One subunit ("rounding subunit") rounds the addition result, and the other subunit ("non-rounding subunit") does not. The result of the rounding subunit is selected as the addition result when one of the following conditions (R1), (R2), (R3) is true: (R1) the operation is an effective addition; (R2) the operation is an effective subtraction, the magnitude ED of the difference between the exponents of the operands is 1, and normalization of the result is not required; (R3) the operation is an effective subtraction and ED>1. The addition result is selected from the non-rounding subunit in the remaining cases. In some embodiments, the rounding subunit overlaps rounding with adding the operands, significands. In some embodiments, the addition unit satisfies ANSI/IEEE Standard 754-1985.

REFERENCES:
patent: H1222 (1993-08-01), Brown et al.
patent: 4217657 (1980-08-01), Handly et al.
patent: 4777613 (1988-10-01), Shahan et al.
patent: 4839846 (1989-06-01), Hirose et al.
patent: 4926369 (1990-05-01), Hokenek et al.
patent: 4926370 (1990-05-01), Brown et al.
patent: 4941120 (1990-07-01), Brown et al.
patent: 4977535 (1990-12-01), Birger
patent: 5117384 (1992-05-01), Drehmel et al.
patent: 5136536 (1992-08-01), Ng
patent: 5204825 (1993-04-01), Ng
patent: 5241490 (1993-08-01), Poon
patent: 5247471 (1993-09-01), Hilker et al.
patent: 5257215 (1993-10-01), Poon
patent: 5260889 (1993-11-01), Palaniswami
patent: 5267186 (1993-11-01), Gupta et al.
patent: 5272660 (1993-12-01), Rossbach
patent: 5282156 (1994-01-01), Miyoshi et al.
patent: 5301139 (1994-04-01), Zinger
patent: 5310134 (1994-05-01), Hsu et al.
patent: 5317527 (1994-05-01), Britton et al.
patent: 5337265 (1994-08-01), Desrosiers et al.
patent: 5343413 (1994-08-01), Inoue
patent: 5357455 (1994-10-01), Sharangpani et al.
patent: 5369607 (1994-11-01), Okamoto
patent: 5390134 (1995-02-01), Heikes et al.
patent: 5463574 (1995-10-01), Desrosiers et al.
patent: 5481686 (1996-01-01), Dockser
patent: 5483476 (1996-01-01), Horen et al.
patent: 5493520 (1996-02-01), Schmookler et al.
patent: 5504912 (1996-04-01), Morinaga et al.
patent: 5511016 (1996-04-01), Bechade
patent: 5528525 (1996-06-01), Suzuki
patent: 5568412 (1996-10-01), Han et al.
Omondi, Amos R., "Computer Arithmetic Systems: Algorithms, Architecture and Implementations", (Prentice-Hall International (UK) Limited, 1994), pp. 76-86.
Yu, Robert K., et al., "167 MHz Radix-4 Floating Point Multiplier", Proceedings of the Twelfth Symposium on Computer Arithmetic (IEEE 1995), pp. 149-154.
Benschneider, et al., "A Pipelined 50-MHz CMOS 64-bit Floating-Point Arithmetic Processor", IEEE Journal of Solid-State Circuits, vol. 24, No. 5, Oct. 1989, pp. 1317-1323.
Quach, et al., "An Improved Algorithm for High-Speed Floating-Point Addition", Stanford University Technical Report No. CSL-TR-90-442, Aug. 1990, pp. 1-17.
Hokenek, et al., "Second-Generation RISC Floating Point with Multiply-Add Fused", IEEE Journal of Soldi-State Circuits, vol. 25, No. 5, Oct. 1990, pp. 1207-1213.
Ide, et al., "A 320-MFLOPS CMOS Floating-Point Processing Unit for Superscalar Processors", IEEE Journal of Solid-State Circuits, vol. 28, No. 3, Mar. 1993, pp. 352-361.
Encyclopedia of Computer Science & Engineering, Second Edition, Van Nostrand Reinhold Co., New York, NY, 1983, pp. 98-102, 1322-1324.
Gwennap, et al., "UltraSparc Unleashes SPARC Performance, Next-Generation Design Could Put Sun Back in Race" Microprocessor Report, vol. 8, No. 13, Oct. 3, 1994, pp. 1-10.
Hokenek et al., "Leading-Zero Anticipator (LZA) in the IBM RISC Systemn/6000 Floating-Point Execution Unit," IBM J. Res. Develop., vol. 34, No. 1, Jan., 1990, pp. 71-77.
Montoye, et al., "Design of the IBM RISC System/6000 Floating Point Execution Unit," IBM J. Res. Develop., vol. 34, No. 1, Jan. 1990, pp. 59-70.
LSI Logic Databook and Design Manual, 5th Ed., HCMOS Macrocells, Macrofunctions, Oct. 1986, pp. 12-1 to 12-28.
Quach et al., "Leading One Prediction -- Implementation, Generalization, and Application, Technical Report: CSL-TR-91-463," Computer Systems Laboratory, Stanford University, Mar. 1991, pp.1-12.
"IEEE Standard for Binary Floating-Point Arithmetic," Institute of Electrical and Electronics Engineers, Inc., New York, NY, ANSI/IEEE Std. 754, Nov. 1994, pp. 1-18.
"IC Master 3. Advertisers Technical Data; LSI Logic Products and Services," Hearst Business Communications, Inc., IC Master, 1991, pp. 3529-3532.
The SPARC Architecture Manual, Version 8, (SPARC International, Inc., Prentice-Hall, Inc., New Jersery, 1992), pp. 1-316.
Kahan, W., et al., "A Porposed IEEE-CS Standard for Binary Floating Point Arithmetic", Proceedings of the Computer Science and Statistics: 12th Annual Symposium on the Interface, May 10-11, 1979, University of Waterloo, Waterloo, Ontario, Canada, pp. 32-36.
Weste, Neil H.E., et al., "Principles of CMOS VLSI Design -- Systems Perspective" (Addison-Wesley Publishing Co., 2nd Ed., 1993), p. 532.
Hicks, T.N., et al., "POWER2 Floating-Point Unit: Architecture and Implementation", IBM J. Res. Develop., vol. 38, No. 5, Sep. 1994, pp. 525-536.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Floating point addition methods and apparatus does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Floating point addition methods and apparatus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Floating point addition methods and apparatus will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-95466

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.