Floating point addition architecture

Details Floating point addition architecture Floating point addition architecture

1982-02-22

1984-12-11

Malzahn, David H.

Boots, shoes, and leggings

G06F 750

Patent

active

044882521

ABSTRACT:
Parallel shifter architecture in an arithmetic unit of a digital computer for processing floating point mantissas. An arithmetic-logic unit (ALU) in series with shifting means functions in parallel with a barrel shifter. Both paths are executed simultaneously and the output of one path is selected for storage at the end of a microcycle based on machine status and the actual floating point numbers manipulated. This architecture provides a significant reduction in floating point addition execution time.

REFERENCES:
patent: 4308589 (1981-12-01), Joyce et al.
patent: 4338675 (1982-07-01), Palmer et al.
patent: 4405992 (1983-09-01), Blau et al.
Smith et al., "Fixed-Point, Floating-Point Adder", Technical Notes RCA Aug. 20, 1969 pp. 1-3.
Covert et al., "Floating-Point Adder Chip Fills Digital-Processing Gap", Electronic Design Nov. 26, 1981 pp. 187-192.

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