Floating-point adder circuit

Details Floating-point adder circuit Floating-point adder circuit

1984-12-28

1988-01-12

Harkcom, Gary V.

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364737, G06F 750, G06F 1100

Patent

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047195894

ABSTRACT:
An arithmetic processing unit executes a first operation to adjust a scale of an exponent part of one data to that of the other data, a second operation to arithmetically calculate the mantissa parts of the two data according to a desired arithmetic operation, and a third operation to correct the exponent part according to the result of the calculation. The arithmetic unit includes an incrementer to increase the exponent part by +1 in parallel with the calculating operation without respect to an overflow resulting from said calculating operation, and a selector to select the output of the incrementer according to the result of the calculation. Therefore, these three operations can be performed at a high speed in only two cycles.

REFERENCES:
patent: 3193669 (1965-07-01), Voltin
patent: 4511990 (1985-04-01), Hagiwara et al.
patent: 4562553 (1985-12-01), Mattedi et al.
patent: 4592006 (1986-05-01), Hagiwara et al.
Smith et al., "Fixed-Point, Floating Point Adder", Technical Notes No.: 846, RCA, Aug. 20, 1969, pp. 1-3.
Hayes, "Computer Architecture and Organization", 1978, pp. 208-209.
Baer, "Computer Systems Architecture", 1980, pp. 122-125.

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