Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2000-07-20
2003-06-17
Malzahn, David H. (Department: 2124)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C708S505000, C345S620000
Reexamination Certificate
active
06581087
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to floating point adders providing an operation performed to compare floating point data in magnitude, and particularly to floating point adders effectively used in clipping in graphics processing.
2. Description of the Background Art
In computer graphics, a clipping is performed to determine whether a coordinate of an object to be displayed exists in a view volume for projective transformation, a displaying window for two-dimensional graphics, and the like. Such clipping is described for example by J. D. Foley et al.,
Computer Graphics: Principles and Practice
, 1992, pp. 271-278, Addison-Wesley Publishing Company, Inc.
Clipping requires an operation performed to compare in magnitude a coordinate of an object to be displayed and a coordinate referred to to provide such clipping.
In general, in computer graphics, floating point data is used as a coordinate, and the coordinate's magnitude is determined by adding or subtracting the floating point data. Such floating point data is added or subtracted according to a process flow, such as described by K. Hwang, translated by Horikoshi,
Rapid Computer Operation System
, pp. 295-299, 1980, Kindaikagakusha, and David A. Patterson and John L. Hennessy,
Computer Architecture A Quantitative Approach
. pp. A-16 to A-21, 1990, Morgan Kaufmann Publishers, Inc.
Throughout the present application, operation devices capable of adding first and second data values together as well as those capable of subtracting the first data value from the second data value will also be referred to as an adder.
Conventionally, a clip code serving as an indicator indicating whether a coordinate of an object to be displayed exists within a displaying window, is generated by a floating point adder.
FIG. 11
is a block diagram for illustrating how a clip code is conventionally generated.
Referring to
FIG. 11
, conventionally a floating point adder
501
and a code generation unit
502
cooperate to generate a clip code CODE.
Floating point adder
501
includes a preprocessing unit
510
receiving an instruction FUNC indicative of operation type and floating point data X and W, a digit match unit
11
matching a digit of floating point data X and that of floating point data W, a fraction part operation unit
12
adding together a fraction part of floating point data X having the digit matched and that of floating point data W having the digit matched or subtracting the fraction part of one data from that of the other data, a normalization unit
13
normalizing a result of an operation performed by fraction part operation unit
12
, and a postprocessing unit
14
responsive to an output from normalization unit
13
for outputting a flag FLAG and an operation result RES.
Code generation unit
502
receives from floating point adder
501
the flag FLAG containing a zero flag, a sign flag and the like and separately performs a logical operation on the zero flag, the sign flag and the like to generate clip code CODE.
FIG. 12
is a block diagram showing a configuration of preprocessing unit
510
shown in FIG.
11
.
As shown in
FIG. 12
, preprocessing unit
510
includes an input verify unit
20
receiving instruction FUNC and two floating point data X and W and generating a special input flag SIF, an exponent part compare unit
21
comparing an exponent part ex of floating point data X and an exponent part ew of floating point data W with each other, a fraction part compare unit
22
comparing a fraction part fx of floating point data X and a fraction part fw of floating point data W with each other, and a select signal generator
24
receiving instruction FUNC, floating point data X and W, an output from exponent part compare unit
21
and an output from fraction part compare unit
22
to generate a select signal SEL for selecting either floating point data X or W to shift selected data to match the digit of floating point data X and that of floating point data W.
Exponent part compare unit
21
compares exponent parts ex and ew. If ex>ew then exponent part compare unit
21
sets a flag F (ex>ew) to 1. If exponent parts ex and ew match then exponent part compare unit
21
sets a flag F (ex==ew) to 1.
Fraction part compare unit
22
compares fraction parts fx and fw. If fx>fw then fraction part compare unit
22
sets a flag F (fx>fw) to 1.
If clipping is herein provided, floating point data X represents a coordinate of an object to be displayed and floating point data W represents a coordinate of a clipping window.
For example, if floating point data X is larger than floating point data W corresponding to a largest coordinate value forming a view volume then an object to be displayed is outside the view volume. As such, clip code CODE is 1. To generate such clip code CODE, initially a floating point subtraction of X−W is performed.
With such operation's result having a zero flag of Z and a sign flag of N, the
FIG. 11
code generation unit
502
provides an NOR of Z and N to find that X>W and thus generate “1” as clip code CODE.
Clipping can also be provided via a dedicated hardware, as described in U.S. Pat. No. 5,157,764.
A conventional clip-code generation technique, as has been shown in
FIGS. 11 and 12
, initially performs a floating-point subtraction process and then uses an operation flag to generate a clip code. As such, the conventional method disadvantageously requires a long process time to generate a clip code. The technique using a dedicated hardware, however, requires disadvantageously increased hardware resources.
SUMMARY OF THE INVENTION
The present invention contemplates a floating point adder capable of rapidly generating a clip code while preventing the circuit from being increased in scale.
The present invention, as briefly described, is a floating point adder including a preprocessing unit, a digit match unit, an operation unit and a normalization unit.
The preprocessing unit receives first and second floating point data and outputs an exponent part comparison result and a fraction part comparison result and a clip code. The preprocessing unit includes an exponent part compare unit comparing an exponent part of the first floating point data and an exponent part of the second floating point data with each other and outputting the exponent part comparison result, a fraction part compare unit comparing a fraction part of the first floating point data and a fraction part of the second floating point data with each other and outputting the fraction part comparison result, and a clip code generation unit receiving the exponent part comparison result and the fraction part comparison result and generating the clip code. The digit match unit refers to the fraction part comparison result and the exponent part comparison result to match a digit of the fraction part of the first floating point data and a digit of the fraction part of the second floating point data. The operation unit adds together the fraction parts of the first and second floating point data having their digits matched by the digit match unit. The normalization unit receives and normalizes a result of an operation performed by the operation unit.
In accordance with the present invention, in another aspect, is a floating point adder including a preprocessing unit, a digit match unit, an operation unit and a normalization unit.
The preprocessing unit receives first and second floating point data and outputs an exponent part comparison result and a fraction part comparison result and a clip code. The preprocessing unit includes an exponent part compare unit comparing an exponent part of the first floating point data and an exponent part of the second floating point data with each other and outputting the exponent part comparison result, a fraction part compare unit comparing a fraction part of the first floating point data and a fraction part of the second floating point data with each other and outputting the fraction part comparison result, an input ve
Inoue Yoshitsugu
Kawai Hiroyuki
Kobara Junko
Streitenberger Robert
Malzahn David H.
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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