Floating point adder

Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

Reexamination Certificate

active

06889241

ABSTRACT:
A floating point adder circuit includes an exponent path and a mantissa path. The exponent path includes a comparator to compare two three-bit exponents. The two exponents are each incremented, and a resultant exponent is chosen from one of the two original exponents or one of the incremented exponents. The mantissa path includes an adder to add mantissas, and an adder bypass path to select one of the mantissas in lieu of performing an addition. The mantissa path also includes constant shifters that conditionally shift the mantissas right by thirty-two bit positions.

REFERENCES:
patent: 5764089 (1998-06-01), Partovi et al.
patent: 5898330 (1999-04-01), Klass
patent: 5900759 (1999-05-01), Tam
patent: 6018756 (2000-01-01), Wolrich et al.
patent: 6175851 (2001-01-01), Iourcha et al.
patent: 6397239 (2002-05-01), Oberman et al.
patent: 6529928 (2003-03-01), Resnick et al.
patent: 6571267 (2003-05-01), Yoshioka
patent: 6578060 (2003-06-01), Chen et al.
Elguibaly, F., “A Fast Parallel Multiplier-Accumulator Using the Modified Booth Algorithm”,IEEE Transactions on Circuits and Systems—II : Analog and Digital Signal Processing, 47(9), pp. 902-908, (Sep. 2000).
Hokenek, E., et al., “Second-Generation RISC Floating Point with Multiply—Add Fused”,IEEE Journal of Solid-State Circuits, 25(5), pp. 1207-1213, (1990).
Luo, Z., et al., “Accelerating Pipelined Integar and Floating-Point Accumulations in Configurable Hardware with Delayed Addition Techniques”,IEEE Transactions on Computers, 49(3), 208-218, (Mar. 2000).
Panneerselvam, G., et al., “Multiply-Add Fused RISC Architectures for DSP Applications”,IEEE Pac Rim, pp. 108-111, (1993).
Beaumont-Smith, A., et al., “Reduced Latency IEEE Floating-Point Standard Adder Architectures”,Proceedings of the 14th IEEE Symposium on Computer Arithmetic, 8 pgs., (1998).
Even, G., et al., “On the Design of IEEE Compliant Floating Point Units”,IEEE Transactions on Computers, vol. 49, 398-413, (May 2000).
Goto, G., et al., “A 54 × 54-b Regularly Structured Tree Multiplier”,IEEE Journal of Solid-State Circuits, vol. 27, 1229-1236, (Sep. 1992).
Ide, N., et al., “2.44-GFLOPS 300-MHz Floating-Point Vector-Processing Unit for High-Performance 3-D Graphics Computing”,IEEE Journal of Solid-State Circuits, vol. 35, 1025-1033, (Jul. 2000).
Klass, F., “Semi-Dynamic and Dynamic Flip-Flops with Embedded Logic”,Proceedings of the Symposium on VLSI Circuits, Digest of Technical Papers, Honolulu, HI, IEEE Circuits Soc. Appl. Phys. Inst. Electron., Inf. & Commun. Eng. Japan, pp. 108-109, (1998).
Lee, K.T., et al., “1 GHz Leading Zero Anticipator Using Independent Sign-Bit Determination Logic”,200 Symposium on VLSI Circuits Digest of Technical Papers, 194-195, (2000).
Partovi, H., et al., “Flow-Through Latch and Edge-Triggered Flip-Flop Hybrid Elements”,Proceedings of the IEEE International Solid-State Circuits Conference, Digest of Technical Papers and Slide Supplement, NexGen Inc., Milpitas, CA, 40 pgs., (1996).

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Floating point adder does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Floating point adder, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Floating point adder will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3454397

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.