Floating-point accumulator

Details Floating-point accumulator Floating-point accumulator

1997-07-28

2000-06-06

Mai, Tan V.

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

708495, G06F 738

Patent

active

060731559

ABSTRACT:
To obtain the sufficiently precise result of floating-point accumulation even if the quantity of computation is enormous, a floating-point accumulator according to the present invention is constituted as follows:
When two floating-point data are stored in any of shift registers, the two data are respectively output to BUS0 and BUS1 via one connected to the shift register of buffers. The two output data are input to an adder via BUS0 and BUS1 and output as added result data after adding the floating-point numbers. The above added result data is returned to each input of the shift registers via BUSW and a multiplexer and written into the shift register corresponding to the addition of the higher level by one of the shift register holding floating-point data before addition. The floating-point numbers are accumulated by repeating the above operation.

REFERENCES:
patent: 4945506 (1990-07-01), Baji et al.
patent: 4949292 (1990-08-01), Hoshino et al.
patent: 5018092 (1991-05-01), Hashimoto
patent: 5307300 (1994-04-01), Komoto
patent: 5359548 (1994-10-01), Yoshizawa et al.
patent: 5757685 (1998-05-01), Ohuchi

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