Floating interruption handling system and method

Details Floating interruption handling system and method Floating interruption handling system and method

1993-04-12

1996-12-03

Sheikh, Ayaz R.

395741, 395727, G06F 1300

Patent

active

055817700

ABSTRACT:
A system and method for handling a floating interruption in a time-saving way and for minimizing the number of signal pins in a multiprocessor system. An interruption is processed in a multiprocessor system including separate FINT line, Control Bus and Data Bus, as well as common ITC. The FINT line transfers a floating interruption request from the ITC to all the processors. The Control Bus transfers an acknowledgement notification of a floating interruption. The Data Bus transfers additional information related to a floating interruption request. A processor 1' starts an acknowledgement and notification process corresponding to its internal state, i.e., a processor in a wait as well as an acknowledgement status for an interruption starts an acknowledgement process for the interruption instantly, while a busy processor delays the process for a given unique cycle and starts the process when it goes to its acknowledgement status.

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