Floating input comparator with precharging of input parasitic ca

Electrical transmission or interconnection systems – Personnel safety or limit control features – Interlock

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Details

307200B, 307246, 307353, 307494, 307577, 307579, 328147, H03K 524, H03K 1716

Patent

active

046111301

ABSTRACT:
The present invention relates to a floating input comparator capable of mitigating the effects of parasitic capacitance present at the input stage of the comparator. In particular, the present invention functions to substantially reduce the effects of parasitic capacitive voltage division present at the nodes interrogated during each detection cycle. In accordance with the present invention, precharging devices (40, 42, 44) are coupled between a predetermined reference potential (VDD) and the affected nodes (D, E, C) to precharge the nodes to the full reference potential prior to each detection cycle, thereby eliminating the effects of a changing, unknown parasitic capacitance at these nodes by replacing an unknown parasitic potential with the known reference potential.

REFERENCES:
patent: 4124806 (1978-11-01), Rusznyak
patent: 4211939 (1980-07-01), Furman
patent: 4214175 (1980-07-01), Chan
patent: 4274013 (1981-06-01), Clemons et al.
patent: 4412143 (1983-10-01), Patella et al.
patent: 4521703 (1985-06-01), Dingwall

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