Floating gate type semiconductor memory device

Details Floating gate type semiconductor memory device Floating gate type semiconductor memory device

1988-10-06

1992-04-21

Wojciechowicz, Edward J.

357 41, 357 45, 357 52, 357 55, 357 2311, H01L 2978

Patent

active

051073137

ABSTRACT:
An EPROM as a nonvolatile semiconductor memory device includes a semiconductor substrate 1, a gate oxide layer 3 formed on the surface of the semiconductor substrate 1, a plurality of floating gates 4a and 4b formed on the gate oxide layer 3 so as to overlap one another at the portions 4ab thereof with a gate oxide layer 14 sandwiched between the overlapping portions 4ab, and control gate strips 5 formed on a gate oxide layer 6 which overlies the floating gates 4a and 4b.

REFERENCES:
patent: 4872041 (1989-10-01), Sugiura et al.
T. Costlow, "Processing Technique Brings EEPROM to Standard Cells", Electronic Design (Oct. 17, 1985), pp. 41 and 42.
Electronics: "E-PROMS Graduate to 256-K Density with Scaled N-Channel Process" by M. Van Buskirk et al, Feb. 24, 1983, pp. 4-113-4-117.

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