Floating gate type nonvolatile semiconductor memory

Details Floating gate type nonvolatile semiconductor memory Floating gate type nonvolatile semiconductor memory

2002-03-27

2003-07-15

Lam, David (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S189020, C365S189090, C365S203000

Reexamination Certificate

active

06594179

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a floating gate type nonvolatile semiconductor memory achieving an improvement in a data write circuit.
2. Description of the Related Art
A floating gate type nonvolatile semiconductor memory assumes a structure achieved by two-dimensionally arraying memory cells each having a control gate electrode and a floating gate electrode embedded in an insulating film laminated one on top of the other. A floating gate type nonvolatile semiconductor memory is used in application as various types of read only memory (ROM) that allow an overwrite.
A floating gate type nonvolatile semiconductor memory in the related art adopts the following structure. A memory cell array is constituted of a plurality of memory cells (MC
0
, MC
1
, . . . ) provided in a matrix pattern, a plurality of bit lines (BL
0
, BL
1
, . . . ) and a plurality of word lines (WL
0
, WL
1
, . . . ) each connected to the individual memory cells. The plurality of word lines are each connected to rows of gate electrodes of the memory cells.
A cell drain voltage source supplies a voltage to be applied to the drain electrode of each of the memory cells (MC
0
, MC
1
, . . . ). A “PGMYB” signal and a “RST” signal which are to be detailed later are input to the cell drain voltage source. In this specification and the attached drawings, the voltage supply terminal at the cell drain voltage source and the voltage supplied through the voltage supply terminal are both referred to as “CDV”, unless otherwise specified.
One CDV supplied from the cell drain voltage source is exclusively connected to the drain electrodes of even-numbered memory cells or odd-numbered memory cells among the memory cells (MC
0
, MC
1
, . . . ) through a plurality of select lines (SL
0
, SL
1
. . . ) in units of individual rows. Another CDV supplied from the cell drain voltage source is connected to the plurality of bit lines (BL
0
, BL
1
, . . . ) sequentially via a data write circuit and a multiplexer circuit. The bit lines (BL
0
, BL
1
, . . . ) are each connected to one row of source electrodes of the memory cells (MC
0
, MC
1
, . . . ).
The data write circuit is employed to write “0” data or “1” data into each memory cell. In addition to the CDV, the “PGMYB” and “RST” signals to be detailed later and the “0” data or the “1” data are input to the data write circuit.
The multiplexer circuit selects a given bit line through which the voltage from the cell drain voltage source is to be supplied and connects the cell drain voltage source to the selected bit line.
Hereafter, “L” indicates the “ground level” and “H” indicates the “source voltage level” in the specification and the attached drawings unless otherwise specified.
The “PGMYB” signal input to the cell drain voltage source and the data write circuit shifts to “L” during a write operation. In addition, the “RST” signal input to the cell drain voltage source and the data write circuit is set to “H” level over a specific period when the “PGMYB” signal shifts from “L” to “H”. The specific length of time over which the “RST” is sustained at “H” level is set to a length of time that is long enough for the voltage at the bit line charged through the write operation to come down to the ground level. A “BLPZA” indicates a node that connects the data write circuit with the multiplexer circuit.
During the write operation, the cell drain voltage source supplies a write voltage, e.g., 4.5V, if “L” is input to a “PGMYB” which is controlled by the “PGMYB” signal. If, on the other hand, “H” is input to the “PGMYB”, a read voltage, e.g., 1.0V, is supplied. In addition, the voltage supply from the cell drain voltage source is suspended while the “RST” signal is at “H”, thereby setting the CDV to the ground level. A low through rate is set for the write voltage (CDV) in order to prevent a write error.
When writing the “0” data, electrons are injected into the floating gate by applying the 4.5V voltage between the drain electrode and the source electrode at the memory cell. However, if the voltage applied between the drain electrode and the source electrode of the memory cell is equal to or lower than 1.5V, no electrons are injected into the floating gate and the “1” data are written. While “0” indicates the state in which a electrons are injected in the following description, it goes without saying that the “0” and “1” settings may be reversed.
Now, a data write operation performed at the MC
0
is explained. The write operation is performed by inputting “L” to the “PGMYB” and applying the 4.5V voltage to the drain electrode of the MC
0
. The multiplexer circuit connects the BL
0
“BLPZA”.
When writing the “1” data, the data write circuit raises the voltage at the “BLPZA” in conformance to the CDV until the voltage is ultimately biased to 3V. As a result, 1.5V is applied between the drain electrode and the source electrode at the MC
0
and no electrons are injected into the floating gate.
When writing the “0” data on the other hand, the data write circuit sets the “BLPZA” to the ground level “L”. Consequently, a 4.5V voltage is applied between the drain electrode and the source electrode at the MC
0
, thereby allowing electrons to be injected into the floating gate of the MC
0
.
During the write operation, the “data write cycle” and the “verify cycle” in which the data that have been written are verified are alternately repeated. When the operation shifts from the data write cycle to the verify cycle, the “PGMYB” signal shifts from “L” to “H”, thereby setting the “RST” signal to “H” over the specific length of time. When the “RST” signal is set to “H”, the data write circuit connects the “BLPZA” to the CDV. Thus, as the CDV shifts to the ground level “L”, the “BLPZA”, too, shifts to the ground level “L”. The data write operation is performed as described above.
As further miniaturization is pursued in semiconductor processes in recent years, the unit length resistance at a bit line has been increasing. This tendency is particularly prominent in a memory with a larger capacity. Since the bit line current generated during a data write operation is significant, the extent to which the voltage becomes lowered through the bit line becomes further pronounced. For this reason, even when the BLPZA is grounded, the voltage is allowed to float by the degree corresponding to the bit line resistance from the ground level at a bit line end distanced from the BLPZA. When this happens, the required level of a voltage is not applied to the drain and the source of the memory cell and, in addition, the difference in the potential between the gate electrode and the source electrode becomes reduced. Thus, a problem arises in that an incomplete write occurs, thereby inducing a write error.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide a floating gate type nonvolatile semiconductor memory that allows a reliable data write and reduces the occurrence of a write error even in a large-capacity memory manufactured through a semiconductor process pursuing further miniaturization by making an improvement on the bit line settings in the related art.
In order to achieve the object described above, in the floating gate type nonvolatile semiconductor memory according to the present invention having a memory cell array constituted of a plurality of memory cells arrayed in a matrix pattern, a plurality of bit lines and a plurality of word lines each connected to the individual memory cells, the plurality of word lines are connected to a row of gate electrodes of memory cells with one voltage supplied from a cell drain voltage source exclusively connected to drain electrodes of even-numbered memory cells or odd-numbered memory cells through a plurality of select lines in units of individual rows, another voltage supplied from the cell drain voltage source is connected to the plurality of bit lines sequentially via a data write circuit and a multiplexer circuit, the bit lines are each connected to a row source electrodes of the

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