Floating-gate semiconductor structures

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C365S185050, C365S185280

Reexamination Certificate

active

07548460

ABSTRACT:
Hot-electron injection driven by hole impact ionization in the channel-to-drain junction of a p-channel MOSFET provides a new mechanism for writing a floating-gate memory. Various pFET floating-gate structures use a combination of this mechanism and electron tunneling to implement nonvolatile analog memory, nonvolatile digital memory, or on-line learning in silicon. The memory is nonvolatile because the devices use electrically isolated floating gates to store electronic charge. The devices enable on-line learning because the electron injection and tunneling mechanisms that write the memory can occur during normal device operation. The memory updates and learning are bidirectional because the injection and tunneling mechanisms add and remove electrons from the floating gate, respectively. Because the memory updates depend on both the stored memory and the pFETs terminal voltages, and because they are bidirectional, the devices can implement on-line learning functions.

REFERENCES:
patent: 3691537 (1972-09-01), Burgess et al.
patent: 3893151 (1975-07-01), Bosselaar
patent: 4087795 (1978-05-01), Rossler
patent: 4216489 (1980-08-01), Clemens et al.
patent: 4420871 (1983-12-01), Scheibe
patent: 4617652 (1986-10-01), Simko
patent: 4622656 (1986-11-01), Kamiya
patent: 4783783 (1988-11-01), Nagai et al.
patent: 4816883 (1989-03-01), Baldi
patent: 4822750 (1989-04-01), Perlegos
patent: 4870555 (1989-09-01), White
patent: 4929988 (1990-05-01), Yoshikawa
patent: 4935702 (1990-06-01), Mead et al.
patent: 4953908 (1990-09-01), Dondlinger
patent: 4953928 (1990-09-01), Anderson
patent: 5010028 (1991-04-01), Gill et al.
patent: 5049515 (1991-09-01), Tzeng
patent: 5059920 (1991-10-01), Anderson
patent: 5068622 (1991-11-01), Mead et al.
patent: 5099156 (1992-03-01), Delbruck
patent: 5103116 (1992-04-01), Sivilotti et al.
patent: 5146106 (1992-09-01), Anderson et al.
patent: 5160899 (1992-11-01), Anderson et al.
patent: 5166562 (1992-11-01), Allen et al.
patent: 5319268 (1994-06-01), Lyon et al.
patent: 5331215 (1994-07-01), Allen et al.
patent: 5336936 (1994-08-01), Allen et al.
patent: 5345418 (1994-09-01), Challa
patent: 5376813 (1994-12-01), Delbruck et al.
patent: 5438542 (1995-08-01), Atsumi et al.
patent: 5463348 (1995-10-01), Sarpeshkar
patent: 5517044 (1996-05-01), Koyama
patent: 5541878 (1996-07-01), LeMoncheck
patent: 5553030 (1996-09-01), Tedrow
patent: 5616942 (1997-04-01), Song
patent: 5627392 (1997-05-01), Diorio et al.
patent: 5633518 (1997-05-01), Broze
patent: 5650346 (1997-07-01), Pan et al.
patent: 5666307 (1997-09-01), Chang
patent: 5677867 (1997-10-01), Hazani
patent: 5687118 (1997-11-01), Chang
patent: 5691939 (1997-11-01), Chang et al.
patent: 5706227 (1998-01-01), Chang et al.
patent: 5710563 (1998-01-01), Vu et al.
patent: 5717636 (1998-02-01), Dallabora et al.
patent: 5734288 (1998-03-01), Dolazza et al.
patent: 5736764 (1998-04-01), Chang
patent: 5761121 (1998-06-01), Chang
patent: 5763912 (1998-06-01), Parat et al.
patent: 5773997 (1998-06-01), Stiegler
patent: 5777361 (1998-07-01), Parris et al.
patent: 5777926 (1998-07-01), Trinh et al.
patent: 5796656 (1998-08-01), Kowshik et al.
patent: 5798967 (1998-08-01), Sarin et al.
patent: 5801994 (1998-09-01), Chang et al.
patent: 5818761 (1998-10-01), Onakado et al.
patent: 5825063 (1998-10-01), Diorio et al.
patent: 5841165 (1998-11-01), Change et al.
patent: 5864242 (1999-01-01), Allen et al.
patent: 5875126 (1999-02-01), Minch et al.
patent: 5898613 (1999-04-01), Diorio et al.
patent: 5901084 (1999-05-01), Ohnakado
patent: 5912842 (1999-06-01), Chang et al.
patent: 5914894 (1999-06-01), Diorio et al.
patent: 5933039 (1999-08-01), Hui et al.
patent: 5939945 (1999-08-01), Thewes et al.
patent: 5944837 (1999-08-01), Talreja et al.
patent: 5966329 (1999-10-01), Hsu et al.
patent: 5969987 (1999-10-01), Blyth et al.
patent: 5972804 (1999-10-01), Tobin et al.
patent: 5982669 (1999-11-01), Kalnitsky et al.
patent: 5982671 (1999-11-01), Kang et al.
patent: 5990512 (1999-11-01), Diorio et al.
patent: 6055185 (2000-04-01), Kalnitsky et al.
patent: 6081451 (2000-06-01), Kalnitsky et al.
patent: 6125053 (2000-09-01), Diorio et al.
patent: 6134182 (2000-10-01), Pilo et al.
patent: 6137721 (2000-10-01), Kalnitsky et al.
patent: 6137722 (2000-10-01), Kalnitsky et al.
patent: 6137723 (2000-10-01), Bergemont et al.
patent: 6137724 (2000-10-01), Kalnitsky et al.
patent: 6144581 (2000-11-01), Diorio et al.
patent: 6166954 (2000-12-01), Chern
patent: 6190968 (2001-02-01), Kalnitsky et al.
patent: 6208557 (2001-03-01), Bergemont et al.
patent: 6222765 (2001-04-01), Nojima
patent: 6222771 (2001-04-01), Tang et al.
patent: 6294427 (2001-09-01), Furuhata et al.
patent: 6294810 (2001-09-01), Li et al.
patent: 6320788 (2001-11-01), Sansbury et al.
patent: 6384451 (2002-05-01), Caywood
patent: 6385090 (2002-05-01), Kitazaki
patent: 6407870 (2002-06-01), Hurevich et al.
patent: 6452835 (2002-09-01), Diorio et al.
patent: 6477103 (2002-11-01), Nguyen et al.
patent: 6479863 (2002-11-01), Caywood
patent: 6534816 (2003-03-01), Caywood
patent: 6563731 (2003-05-01), Bergemont
patent: 6580642 (2003-06-01), Wang
patent: 6678190 (2004-01-01), Yang et al.
patent: 2003/0206437 (2003-11-01), Diorio et al.
patent: 2004/0004861 (2004-01-01), Srinivas et al.
patent: 2004/0021166 (2004-02-01), Hyde et al.
patent: 2004/0037127 (2004-02-01), Lindhorst et al.
patent: 2004/0052113 (2004-03-01), Diorio et al.
patent: 0 298 618 (1989-01-01), None
patent: 0 562 257 (1993-09-01), None
patent: 0 776 049 (1997-05-01), None
patent: 0 778 623 (2001-07-01), None
patent: 00/38239 (2000-06-01), None
patent: 00/60672 (2000-10-01), None
Carley, L. Richard, “Trimming Analog Circuits Using Floating-Gate Analog MOS Memory”, IEEE Journal of Solid-State Circuits, vol. 24, No. 6, Dec. 1989, pp. 1569-1575.
Diorio, et al., “Adaptive CMOS: From Biological Inspiration to Systems-on-a-Chip”; IEEE, vol. 90, No. 3; Mar. 2002; pp. 345-357.
Diorio, et al., “A Floating-Gate MOS Learning Array with Locally Computed Weight Updates” IEEE Transactions on Electron Devices, vol. 44, No. 12, Dec. 1997, pp. 1-10.
Diorio, et al., “A High-Resolution Non-Volatile Analog Memory Cell”, IEEE, 1995, pp. 2233-2236.
Diorio, “A p-Channel MOS Synapse Transistor with Self-Convergent Memory Writes”, IEEE Transaction On Electron Devices, vol. 47, No. 2, pp. 464-472, Feb. 2000.
International Search Report, Application No. PCT/US 03/21677, date of mailing Dec. 2, 2003.
Fujita et al., A Floating Gate Analog Memory Device for Neural Networks, IEEE, vol. 40, No. 11, pp. 2029-2035, 1993.
Gray, et al., “Analysis and Design of Analog Integrated Circuits”, Second Edition, University of California, Berkeley, 1984, pp. 66-71.
Hasler, et al., “Single Transistor Learning Synapses”, Cambridge, MA, The MIT Press, 1995, pp. 817-824.
Hasler, et al., “Single Transistor Learning Synapse with Long Term Storage”, IEEE, 1995, pp. 1660-1663.
Hasler, et al., “An autozeroing Floating-Gate Amplifier”, IEEE Journal of Solid State Circuits, Draft Copy, pp. 1-15.
Hochet, et al., “Implementation of a Learning Kohonen Neuron Based on a New Multilevel Storage Technique”, IEEE Journal of Solid-State Circuits, vol. 26, No. 3, Mar. 1991, pp. 262-267.
Hollis, et al., “A Neural Network Learning Algorithm Tailored for VLSI Implementation”, IEEE Transactions on Neural Networks, vol. 5, No. 5, Sep. 1994, pp. 784-791.
Hu, et al., “Hot-Electron-Induced MOSFET Degradation-Model, Monitor, and Improvement”, IEEE Transactions on Electron Devices, vol. ED-32, No. 2, Feb. 1985, pp. 375-385.
Ismail, et al., “Neural Information Processing II”, Analog VLSI Signal and Information Processing, 1994, pp. 358-413.
Johnson, R. Colin, “Mead Envisions New Design Era”, Electronic Engineering Times, Jul. 17, 1995, p. 1, 37 and 38.
Johnson, R. Colin, “Neural Team Bares Silicon Brain”, Electronic Engineering Times, Jul. 3, 1995, pp. 1, 31.
Lazzaro, et al., “Systems

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Floating-gate semiconductor structures does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Floating-gate semiconductor structures, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Floating-gate semiconductor structures will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4146361

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.