Floating gate semiconductor nonvolatile memory having impurity d

Details Floating gate semiconductor nonvolatile memory having impurity d Floating gate semiconductor nonvolatile memory having impurity d

1992-07-20

1993-11-16

Gossage, Glenn

Static information storage and retrieval

Floating gate

Particular biasing

365178, 365184, 257316, 257326, 257315, G11C 1604, H01L 29788

Patent

active

052629872

ABSTRACT:
A semiconductor nonvolatile memory has a base semiconductor region of one conductivity type. A first semiconductor region of the one conductivity type is formed in a surface portion of the base semiconductor region and has an impurity density higher than that of the base semiconductor region. A source region and a drain region of opposite conductivity than the first semiconductor region are formed in a surface portion of the first semiconductor region in spaced relation from each other. A second semiconductor region of the one conductivity type is formed in a surface portion of the first semiconductor region and contains an impurity of the opposite conductivity type. A floating gate electrode is formed over and electrically insulated from the second semiconductor region, and a control gate electrode is formed over and electrically insulated from the floating gate electrode. The control gate may include a section which is formed over a portion of a channel region between the source and drain regions, and a third semiconductor region may be formed below this section of the control gate. The semiconductor nonvolatile memory has a lowered threshold voltage and is operative at low drive voltages and at high speed while maintaining high programming performance and memory cell separation or isolation.

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patent: 5014097 (1991-05-01), Kazerounian et al.
Wada et al, "Limiting Factors for Programming EPROM of Reduced Dimensions," Int'l. Electron Devices Meeting (IEDM), Digest of Tech. Papers, 1980, pp. 38-41.

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