Floating gate programmable cell array for standard CMOS

Details Floating gate programmable cell array for standard CMOS Floating gate programmable cell array for standard CMOS

2001-12-05

2004-03-09

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Floating gate

C365S149000, C365S185050

Reexamination Certificate

active

06704221

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to a floating gate programmable device circuit, and more particularly, to a floating gate device using charge injection.
(2) Description of the Prior Art
EEPROM, Flash, and other programmable devices are integrated onto integrated circuit devices commonly in the art. These devices present several difficulties for integration. One of the chief problems is that the programming voltages are typically much larger than the operation voltages of the typical device technologies. For example, a 0.35 micron CMOS technology may have an operating voltage of between about 3 Volts and about 5 Volts. The gate breakdown voltage is about 7.5 Volts for a gate oxide thickness of about 7.5 nanometeres. Meanwhile the programming voltage for an EEPROM cell may be greater than about 11 Volts.
To provide some form of integrated circuit programmability, fuse devices are sometimes used. A fuse device, typically of polysilicon, can be selectively blown or not blown during a programming operation. This approach only provides a one-time programmability for the integrated circuit device. Providing a programmable device that can be re-programmed and that is programmable with low voltage CMOS circuitry represents a needed advancement in the art.
Several prior art inventions describe nonvolatile storage devices. U.S. Pat. No. 5,835,402 to Rao et al describes circuits for non-volatile storage on a CMOS IC. Low voltage devices are used to program and erase cells using high voltage. U.S. Pat. No. 5,663,907 to Frayer et al teaches a circuit for programming EEPROM cells with high voltage. In addition, Ohsaki et al, “A Single Poly EEPROM Cell Structure for Use in Standard CMOS Processes,” Journal of Solid-State Circuits, Vol. 29, No. 3, pp. 311-316, discloses a nonvolatile device structure. In Harrison et al, “A CMOS Programmable Analog Memory-Cell Array Using Floating-Gate Circuits, IEEE Transactions on Circuits and Systems II, Vol. 48, No. 1, 2001, pp. 4-11, nonvolatile “e-pots” are described. Finally, in Hasler et al, “Overview of Floating-Gate Devices, Circuits, and Systems,” IEEE Transactions on Circuits and Systems II, Vol. 48, No. 1, 2001, pp. 1-3, several floating gate devices and applications are disclosed.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable floating gate programmable device circuit.
A further object of the present invention is to provide a floating gate programmable device which can be programmed using low voltage CMOS devices.
Another still further object of the present invention is to provide a floating gate programmable device which can be integrated into a standard CMOS process.
In accordance with the objects of this invention, a floating gate programmable device cell is achieved. The device comprises, first, a negative injection transistor having drain, source, bulk, and gate. The source and bulk are coupled to ground. The drain forms an output of the cell. A positive injection transistor has drain, source, bulk, and gate. The drain, source, and bulk are coupled to a programming voltage. The gate is coupled to the negative injection transistor gate to form a floating gate node. Finally, a capacitor has a first terminal coupled to the floating gate node and a second terminal coupled to a control voltage. The states of the programming voltage and the control voltage determine negative charge injection onto the floating gate node and positive charge injection onto the floating gate node. A voltage on the floating gate node comprises a nonvolatile memory state that is detectable by the impedance of the output.


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Ohsaki et al., “A Single Poly EEPROM Cell Structure for Use in Standard CMOS Processes,” Journal of Solid-State Circuits, vol. 29, No. 3, Mar. 1994, pp. 311-316.
Harrison et al., “A CMOS Programmable Analog Memory -Cell Array Using Floating-Gate Circuits”, IEEE Transactions on Circuits and Systems II, vol. 48, No. 1, Jan. 2001, pp. 4-11.
Hasler et al., “Overview of Floating-Gate Devices, Circuits, and Systems, ” IEEE Transactions on Circuits and Systems II, vol. 48, No. 1, Jan. 2001, pp. 1-3.

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