Floating gate process methodology

Details Floating gate process methodology Floating gate process methodology

2006-12-21

2010-06-29

Nguyen, Thanh (Department: 2893)

Semiconductor device manufacturing: process

With measuring or testing

C438S593000, C257SE29129

Reexamination Certificate

active

07745236

ABSTRACT:
A method of deprocessing a semiconductor structure is provided. The method involves removing a silicide layer over a second poly layer, an interpoly dielectric layer, a first poly layer, an optionally an oxide layer on a substrate. The method may further involve at least one of removing a second poly layer, removing an interpoly dielectric layer, removing a first poly layer, removing an oxide layer, and removing an unimplanted portion of a substrate. The exposed layer/portion of the semiconductor structure can be subjected to an inspection for defects and/or other characteristics. The inspection can aid in defect reduction strategies, among other things, when applied to new technology ramp, monitoring of baseline wafer starts, customer returns, etc.

REFERENCES:
patent: 4623255 (1986-11-01), Suszko
patent: 4902379 (1990-02-01), Rhodes
patent: 6210994 (2001-04-01), Calegari et al.
patent: 6861005 (2005-03-01), Brask
patent: 2003/0214002 (2003-11-01), Chow et al.

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