Floating gate nonvolatile memory with distributed blocking featu

Details Floating gate nonvolatile memory with distributed blocking featu Floating gate nonvolatile memory with distributed blocking featu

1992-06-19

1993-11-30

LaRoche, Eugene R.

Static information storage and retrieval

Floating gate

Particular biasing

36523003, 365218, 36518901, G11C 1700

Patent

active

052671968

ABSTRACT:
A nonvolatile memory device residing on a substrate is described. The memory device includes a first block and a second block. The first block includes a first sub-block comprising a first memory cell, a first bit line coupled to a drain of the first memory cell, and a first source line coupled to a source of the first memory cell. The first block also includes a second sub-block which includes a second memory cell, a second bit line coupled to a drain of the second memory cell, and a second source line coupled to a source of the second memory cell. The second block comprises a third sub-block comprising a third memory cell, a third bit line coupled to a drain of the third memory cell, and a third source line coupled to a source of the third memory cell. The second block also includes a fourth sub-block which includes a fourth memory cell, a fourth bit line coupled to a drain of the fourth memory cell, and a fourth source line coupled to a source of the fourth memory cell. The first sub-block of the first block and the third sub-block of the second block are grouped together on the substrate to form a first data bit group corresponding to a first data pin of the memory device such that the distances of the first and third memory cells of the first data bit group to a first sensing circuit are substantially minimized and are substantially equal. The second sub-block of the first block and the fourth sub-block of the second block are grouped together on the substrate to form a second data bit group corresponding to a second data pin of the memory device such that the distances of the second and fourth memory cells of the second data bit group to a second sensing circuit are substantially minimized and are substantially equal.

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patent: 4967399 (1990-10-01), Kuwabara et al.
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patent: 4977538 (1990-12-01), Anami et al.
patent: 5065364 (1991-11-01), Atwood et al.

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