Floating gate nonvolatile memory with configurable erasure block

Details Floating gate nonvolatile memory with configurable erasure block Floating gate nonvolatile memory with configurable erasure block

1992-06-19

1994-01-18

LaRoche, Eugene R.

Static information storage and retrieval

Floating gate

Particular biasing

365218, 36523003, 36518901, G11C 1134

Patent

active

052804470

ABSTRACT:
A nonvolatile memory includes a first block and a second block. The first block comprises a first memory cell and a first source line coupled to a source of the first memory cell. The second block comprises a second memory cell and a second source line coupled to a source of the second memory cell. A first source switch is coupled to the first source line for selectively coupling a first potential, a second potential, and a third potential to the first source line. The second potential has a voltage intermediate between the first potential and the third potential. A second source switch is coupled to the second source line for selectively coupling one of the first, second, and third potentials to the second source line. A block select circuit receives a block address for selecting one of the first and second source switches to couple one of the first, second, and third potentials to its respective one of the first and second source lines. A configuration cell is coupled to the block select circuit for configuring block operations of the first and second blocks. When the configuration cell is in a first voltage state, the configuration cell causes the block select circuit to separately select one of the first and second source switches depending upon the address received. When the configuration cell is in a second voltage state, the configuration cell causes the block select circuit to collectively select the first and second source switches.

REFERENCES:
patent: 4849943 (1989-07-01), Pfennings
patent: 4939696 (1990-07-01), Katsuo et al.
patent: 4949309 (1990-08-01), Rao
patent: 4958326 (1990-09-01), Sakurai
patent: 4961164 (1990-10-01), Miyoaka et al.
patent: 4967399 (1990-10-01), Kuwabara et al.
patent: 4977538 (1990-12-01), Anami et al.
patent: 5020026 (1991-05-01), Schreck et al.
patent: 5065364 (1991-11-01), Atwood et al.

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