Floating gate non-volatile memory with deep power down and write

Details Floating gate non-volatile memory with deep power down and write Floating gate non-volatile memory with deep power down and write

1991-10-09

1993-03-23

LaRoche, Eugene R.

Static information storage and retrieval

Powering

Conservation of power

365185, 365228, G11C 1100

Patent

active

051970341

ABSTRACT:
A non-volatile memory is described. The memory includes a memory array that includes a main block and a boot block. The memory also includes a control input for receiving a control signal. The control signal can be in a first voltage state, a second voltage state, and a third voltage state. Circuitry means is coupled to receive the control signal at the control input for (1) allowing the boot block to be updated when the control signal is in the first state and for (2) generating a power off signal to switch the memory into a substantially powered off state when the control signal is in the third voltage state. A method of controlling a non-volatile memory is also described.

REFERENCES:
patent: 4387449 (1983-06-01), Masuda
patent: 4718043 (1988-01-01), Akatsuka
patent: 4906862 (1990-03-01), Itano et al.
patent: 5084843 (1992-01-01), Mitsuishi et al.
patent: 5113373 (1992-05-01), Lee

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