Floating gate non-volatile memory with blocks and memory refresh

Details Floating gate non-volatile memory with blocks and memory refresh Floating gate non-volatile memory with blocks and memory refresh

1990-12-28

1993-08-24

Fears, Terrell W.

Static information storage and retrieval

Floating gate

Particular biasing

365222, G11C 1300, G11C 1140

Patent

active

052395057

ABSTRACT:
A non-volatile memory device is described. The memory device includes a first block and a second block. The first block includes a first memory cell having a drain region, a source region, a floating gate, and a control gate. A first word line is coupled to the control gate of the first memory cell. The second block includes a second memory cell having a drain region, a source region, a floating gate, and a control gate. A second word line is coupled to the control gate of the second memory cell. A bit line is coupled to the drain region of the first and the second memory cell. A refresh control means performs a refresh operation on one of the first and second memory cell. A sensing means is coupled to the bit line, and has a first reference potential and a second reference potential for detecting a voltage state of the first and second memory cell during the refresh operation. When the voltage state is detected to fall between the first reference potential and the second reference potential, the sensing means generates a refresh signal to the refresh control means. When the refresh control means receives the refresh signal from the sensing means, the voltage state is raised above the second reference potential. A method of refreshing the non-volatile device is also described.

REFERENCES:
patent: 5043939 (1991-08-01), Slamowitz et al.
"21464 65,536.times.4 Dynamic RAM," Memory Components Handbook, pp. 3-58 through 3-71 (Intel Corp. Sep. 1989).

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