Static information storage and retrieval – Floating gate – Particular biasing
Patent
1990-12-21
1993-09-14
LaRoche, Eugene R.
Static information storage and retrieval
Floating gate
Particular biasing
36523003, G11C 800
Patent
active
052455700
ABSTRACT:
A non-volatile memory device is described. The memory device includes a global bit line, a first block, and a second block. The first block includes a first memory cell having a drain region, a source region, a floating gate and a control gate. A first word line is coupled to the control gate of the first memory cell. A first local bit line is coupled to the drain region of the first memory cell. A first selecting means couples the first local bit line to the global bit line. The second block includes a second memory cell having a drain region, a source region, a floating gate and a control gate. A second word line is coupled to the control gate of the second memory cell. A second local bit line is coupled to the drain region of the second memory cell. A second selecting means couples the second local bit line to the global bit line.
REFERENCES:
patent: 4849943 (1989-07-01), Pfennings
patent: 4939696 (1990-07-01), Katsuo et al.
patent: 4958326 (1990-09-01), Sakurai
patent: 4961164 (1990-10-01), Miyaoka et al.
patent: 4967399 (1990-10-01), Kuwabara et al.
patent: 4977538 (1990-12-01), Anami et al.
patent: 5065364 (1991-11-01), Atwood et al.
Atwood Gregory E.
Baker Alan E.
Fazio Albert
Mielke Neal R.
Intel Corporation
LaRoche Eugene R.
Nguyen Tan
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