Floating gate memory with sidewall tunnelling area

Details Floating gate memory with sidewall tunnelling area Floating gate memory with sidewall tunnelling area

1989-07-14

1990-06-05

Larkins, William D.

Static information storage and retrieval

Magnetic bubbles

Guide structure

357 233, 365185, H01L 2704, H01L 2978, G11C 1140

Patent

active

049318470

ABSTRACT:
The tunnelling area of a EEPROM memory device of the FLOTOX type is efficiently reduced in respect of the minimum areas obtained by means of current fabrication technologies, by forming the injection zone for the transfer of the electric charges by tunnel effect to an from the floating gate through an original self-aligned process, which allows to limit the dimensions of such a tunnelling area independently from the resolution limits of the available photolithographic technology.

REFERENCES:
patent: 4132904 (1979-01-01), Harari
patent: 4477825 (1984-10-01), Yaron et al.
patent: 4608585 (1986-08-01), Keshtbod
patent: 4701776 (1987-10-01), Perlegos et al.
patent: 4754320 (1988-06-01), Mizutani et al.

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