Floating gate memory device with interpoly charge trapping...

Details Floating gate memory device with interpoly charge trapping... Floating gate memory device with interpoly charge trapping...

2009-03-24

2011-11-29

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C257S315000, C257SE29309, C257SE21422, C257SE21423, C365S185180

Reexamination Certificate

active

08068370

ABSTRACT:
A charge trapping floating gate is described with asymmetric tunneling barriers. The memory cell includes a source region and a drain region separated by a channel region. A first tunneling barrier structure is disposed above the channel region. A floating gate is disposed above the first tunneling barrier structure covering the channel region. A second tunneling barrier is disposed above the floating gate. A dielectric charge trapping structure disposed above the second tunneling barrier and a blocking dielectric structure is disposed above the charge trapping structure. A top conductive layer disposed above the top dielectric structure acts as a gate. The second tunneling barrier is a more efficient conductor of tunneling current, under bias conditions applied for programming and erasing the memory cell, than the first tunneling barrier structure.

REFERENCES:
patent: RE31083 (1982-11-01), DeKeersmaecker et al.
patent: 4630086 (1986-12-01), Sato et al.
patent: 5286994 (1994-02-01), Ozawa et al.
patent: 5319229 (1994-06-01), Shimoji et al.
patent: 5851881 (1998-12-01), Lin et al.
patent: 5952692 (1999-09-01), Nakazato et al.
patent: 6011725 (2000-01-01), Eitan et al.
patent: 6026026 (2000-02-01), Chan et al.
patent: 6074917 (2000-06-01), Chang et al.
patent: 6169693 (2001-01-01), Chan et al.
patent: 6218700 (2001-04-01), Papadas et al.
patent: 6469343 (2002-10-01), Miura et al.
patent: 6512696 (2003-01-01), Fan et al.
patent: 6521943 (2003-02-01), Mine et al.
patent: 6605840 (2003-08-01), Wu et al.
patent: 6709928 (2004-03-01), Jenne et al.
patent: 6720630 (2004-04-01), Mandelman et al.
patent: 6740928 (2004-05-01), Yoshii et al.
patent: 6784480 (2004-08-01), Bhattacharyya
patent: 6815764 (2004-11-01), Bae et al.
patent: 6818558 (2004-11-01), Rathor et al.
patent: 6858906 (2005-02-01), Lee et al.
patent: 6897533 (2005-05-01), Yang et al.
patent: 6912163 (2005-06-01), Zheng et al.
patent: 6977201 (2005-12-01), Jung et al.
patent: 7033956 (2006-04-01), Wu
patent: 7075828 (2006-07-01), Lue et al.
patent: 7115469 (2006-10-01), Halliyal et al.
patent: 7115942 (2006-10-01), Wang
patent: 7133313 (2006-11-01), Shih et al.
patent: 7151692 (2006-12-01), Wu
patent: 7164603 (2007-01-01), Shih et al.
patent: 7187590 (2007-03-01), Zous et al.
patent: 7190614 (2007-03-01), Wu
patent: 7209390 (2007-04-01), Lue et al.
patent: 7442988 (2008-10-01), Oh et al.
patent: 7473589 (2009-01-01), Lai et al.
patent: 7646056 (2010-01-01), Choi et al.
patent: 7961525 (2011-06-01), Osame et al.
patent: 2003/0025147 (2003-02-01), Nomoto et al.
patent: 2003/0030100 (2003-02-01), Lee et al.
patent: 2003/0032242 (2003-02-01), Lee et al.
patent: 2003/0042534 (2003-03-01), Bhattacharyya
patent: 2003/0047755 (2003-03-01), Lee et al.
patent: 2003/0146465 (2003-08-01), Wu
patent: 2003/0224564 (2003-12-01), Kang et al.
patent: 2004/0079983 (2004-04-01), Chae et al.
patent: 2004/0108512 (2004-06-01), Iwata et al.
patent: 2004/0183126 (2004-09-01), Bae et al.
patent: 2004/0251489 (2004-12-01), Jeon et al.
patent: 2004/0256679 (2004-12-01), Hu
patent: 2005/0006696 (2005-01-01), Noguchi et al.
patent: 2005/0023603 (2005-02-01), Eldridge et al.
patent: 2005/0062098 (2005-03-01), Mahajani et al.
patent: 2005/0074937 (2005-04-01), Jung
patent: 2005/0093054 (2005-05-01), Jung
patent: 2005/0219906 (2005-10-01), Wu
patent: 2005/0237801 (2005-10-01), Shih
patent: 2005/0237809 (2005-10-01), Shih et al.
patent: 2005/0237813 (2005-10-01), Zous et al.
patent: 2005/0237815 (2005-10-01), Lue et al.
patent: 2005/0237816 (2005-10-01), Lue et al.
patent: 2005/0270849 (2005-12-01), Lue
patent: 2005/0281085 (2005-12-01), Wu
patent: 2006/0088983 (2006-04-01), Fujisawa et al.
patent: 2006/0118858 (2006-06-01), Jeon et al.
patent: 2006/0124991 (2006-06-01), Ohba
patent: 2006/0198189 (2006-09-01), Lue et al.
patent: 2006/0198190 (2006-09-01), Lue
patent: 2006/0202252 (2006-09-01), Wang et al.
patent: 2006/0202261 (2006-09-01), Lue et al.
patent: 2006/0258090 (2006-11-01), Bhattacharyya et al.
patent: 2006/0261401 (2006-11-01), Bhattacharyya
patent: 2006/0281260 (2006-12-01), Lue
patent: 2007/0012988 (2007-01-01), Bhattacharyya
patent: 2007/0029625 (2007-02-01), Lue et al.
patent: 2007/0031999 (2007-02-01), Ho et al.
patent: 2007/0045718 (2007-03-01), Bhattacharyya
patent: 2007/0047303 (2007-03-01), Kim
patent: 2007/0069283 (2007-03-01), Shih et al.
patent: 2007/0120179 (2007-05-01), Park et al.
patent: 2007/0138539 (2007-06-01), Wu et al.
patent: 2007/0268753 (2007-11-01), Lue et al.
patent: 2008/0067577 (2008-03-01), Wang et al.
patent: 2008/0081462 (2008-04-01), Choi
patent: 2008/0099830 (2008-05-01), Lue et al.
patent: 2008/0116506 (2008-05-01), Lue
patent: 2009/0021979 (2009-01-01), Sung et al.
patent: 2009/0039417 (2009-02-01), Chen et al.
patent: 0016246 (1980-10-01), None
patent: 1411555 (2004-04-01), None
patent: 01677311 (2006-07-01), None
patent: 01677312 (2006-07-01), None
patent: 59074680 (1984-04-01), None
patent: 11040682 (1999-02-01), None
patent: 2004363329 (2004-12-01), None
patent: 2005184029 (2005-07-01), None
patent: 2006190990 (2006-07-01), None
patent: 1020060106298 (2006-10-01), None
patent: 10088202 (2008-04-01), None
Search Report mailed Aug. 26, 2010 in European Application No. 09158082.9, 7 pages.
Aminzadeh et al., “Conduction and Charge Trapping in Polysilicon-Silicon Nitride-Oxide-Silicon Structures under Positive Gate Bias,” IEEE Trans. on Electron Dev. 35(4) Apr. 1998 459-467.
Baik, Seung, et al., “High Speed and Nonvolatile Si Nanocrystal Memory for Scaled Flash Technology using Highly Field-Sensitive Tunnel Barrier,” IEEE IEDM 03-545 22.3.1-22.3.4.
Blomme et al., “Multilayer tunneling barriers for nonvolatile memory applications,” Device Research Conf, 2002 60th DRC Digest 153-154.
Blomme et al., “Write/Erase Cycling Endurance of Memory Cells with SiO2/HfO2 Tunnel Dielectric,” IEEE Trans. on Dev. and Mterials Reliability 4(3), Sep. 2004 345-351.
Buckley, J., et al., “Engineering of ‘Conduction Band-Crested Barriers’ or ‘Dielectric Constant-Crested Barriers’ in view of their application of floating-gate non-volatile memory devices,” VLSI 2004, 55-56.
Chindalore, et al., “A New Combination-Erase Technique for Erasing Nitride Based (SONOS) Nonvolatile Memories,” IEEE Electron Dev. Lett. 24(4) Apr. 2003, 257-259.
Cho, et al., “Simultaneous Hot-Hole Injection at Drain and Source for Efficient Erase and Excellent Endurance in SONOS Flash EEPROM Cells,” IEEE Electron Device Letters, vol. 24, No. 4, Apr. 2003, 260-262.
DiMaria, D.J., et al., “Conduction Studies in Silicon Nitride: Dark Currents and Photocurrents,” IBM J. Res. Dev. May 1977, 227-244.
Eitan, et al., “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell,” IEEE Electron Device Lett 21(11) Nov. 2000, 543-545.
Govoreanu et al., “An Investigation of the Electron Tunneling Leakage Current Through Ultrathin Oxides/High-k Gate Stacks at Inversion Conditions,” IEEE SISPAD Intl. Conf. Sep. 3-5, 2003 287-290.
Govoreanu et al., “Simulation of Nanofloating Gate Memory with High-k Stacked Dielectrics,” IEEE SISPAD Intl. Conf. Sep. 3-5, 2003 299-302.
Govoreanu et al., “VARIOT: A Novel Multilayer Tunnel Barrier Concept for Low-Voltage Nonvolatile Memory Devices,” IEEE Electron Dev. Lett. 24(2) Feb. 2003 94-10.
Hijiya, S., et al., “High-Speed Write/Erase EAROM Cell with Graded Energy Band-Gap Insulator,” Electronics and Communications in Japan, Part 2, vol. 68, No. 2, Jun. 6, 1984, 28-36.
Hinkle, C.L., et al., “Enhanced tunneling in stacked gate dielectrics with ultra-thin HfO2 (ZrO2) layers sandwiched between thicker SiO2 layers,” Surface Science, Sep. 20, 2004, vol. 566-568, 1185-1189.
Ito, et al., “A Novel MNOS Technology Using Gate Hole Injection in Erase Operation for Embedded Nonvolatile Memory Applications.” 2004 Symp. on VLSI Tech Dig. of Papers 2004, 80-81.
Kim et al., “Robust Multi-Bit Programmable Flash Mem

Affiliated with

Also associated with

Rating

Floating gate memory device with interpoly charge trapping... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Floating gate memory device with interpoly charge trapping..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Floating gate memory device with interpoly charge trapping... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4286823