Floating gate memory cell array allowing cell-by-cell erasure

Details Floating gate memory cell array allowing cell-by-cell erasure Floating gate memory cell array allowing cell-by-cell erasure

1996-11-27

1999-10-12

Zarabian, A.

Static information storage and retrieval

Floating gate

Particular biasing

36518528, G11C 1134

Patent

active

059663324

ABSTRACT:
A non-volatile semiconductor memory device includes a plurality of memory cells. Each of the plurality of memory cells has a control gate, a source, a drain and a floating gate for storing charges. The floating gate is preferably capacitively coupled to at least one of the source and the drain. The memory device also includes a control circuit for controlling voltages that are respectively applied to the control gate, the source and the drain in order to execute an erasure operation of at least one memory cell in a "memory cell-by-memory cell" format.

REFERENCES:
patent: 4698787 (1987-10-01), Mukherjee
patent: 5202850 (1993-04-01), Jenq
patent: 5491656 (1996-02-01), Sawada
patent: 5557572 (1996-09-01), Sawada
patent: 5583812 (1996-12-01), Harari
patent: 5598369 (1997-01-01), Chen
patent: 5644532 (1997-07-01), Chang
The Institute of Electronics, Information and Communication Engineers, "A Bit Erasable Flash EEPROM Technology with a Single Floating Gate Transistor Memory Cell" Technical Report of IEICE, SDM93-23, (1993-05), pp. 9-14.

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