Floating-gate memory cell

Details Floating-gate memory cell Floating-gate memory cell

1982-09-20

1986-06-24

Edlow, Martin H.

Static information storage and retrieval

Magnetic bubbles

Guide structure

357 54, 357 41, 365185, H01L 2978, G11C 1134

Patent

active

045970009

ABSTRACT:
A memory cell includes a selection transistor and a memory transistor formed as insulated gate field effect transistors. The transistors are formed on a substrate with a channel for the selection transistor coupled to a channel for the memory transistor. A layer of oxide overlies both transistors. The channels are formed between a programming line and a reading line formed in the substrate. A thin film window in the oxide overlies a region of the programming line. An insulated, floating gate is formed overlying the window and the channel of the memory transistor. A gate electrode overlies the floating gate and the channel of the selection transistor.

REFERENCES:
patent: 4016588 (1977-04-01), Ohya et al.
patent: 4305083 (1981-12-01), Gutierrez
patent: 4412311 (1983-10-01), Miccoli et al.
patent: 4451904 (1984-05-01), Sugiura
IEEE Transactions on Electron Devices, vol. ED. 24, #5, May 1977, pp. 594-599, by Gosney.
IBM Technical Disclosure Bulletin "Electrically Rewritable Nonvolatile Memory", vol. 16, #2, Jul. 73; James.
IBM Technical Disclosure Bulletin, vol. 16, #2, Jul. 73, "Floating Gate FET Memory" by Chiu, Pan, Tsang.
IBM Technical Disclosure Bulletin by vol. 17, #8, Jan. 75, "Electrically Erasable Floating Gate", FET Memory Cell, Anantha.
Electronic Design, Nov. 8, 1980--Tom Williams "Memory, GaAs Technologies Keep Improving".

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