Floating gate memory array with latches having improved immunity

Details Floating gate memory array with latches having improved immunity Floating gate memory array with latches having improved immunity

1992-11-12

1994-11-29

Nguyen, Viet Q.

Static information storage and retrieval

Floating gate

Particular biasing

365182, 36518905, 36523008, 3652385, G11C 700, G11C 800

Patent

active

053696093

ABSTRACT:
An electrically programmable and erasable floating gate memory device has two substantially identical sections. Each section has a plurality of column address lines, a plurality of row lines and a plurality of source lines. A first plurality of floating gate memory cells has its drain connected to a different one of the column address line, its gate connected to the same first row line and its source connected to the same first source line. A second plurality of floating gate memory cells has its drain connected to a different one of the column address line, its gate connected to the same second row line, different from the first row line, and its source connected to the same first source line. Associated with each section is a plurality of bit latches, one for each column. Reprogramming data is stored in the bit latches. Data from the bit latches of one section are stored in the first plurality of floating gate memory cells. Data from the bit latches of the other section are stored in the second plurality of floating gate memory cells.

REFERENCES:
patent: 4698787 (1987-10-01), Mukherjee et al.
patent: 4785424 (1988-11-01), Lin et al.
patent: 4887242 (1989-12-01), Hashimoto
patent: 5029130 (1991-07-01), Yeh
patent: 5101379 (1992-03-01), Lin et al.
patent: 5218569 (1993-06-01), Banks
U.S. Ser. No. 07/682,459 filed on Apr. 9, 1991, Yeh et al.

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