Floating gate memory array device having improved immunity to wr

Details Floating gate memory array device having improved immunity to wr Floating gate memory array device having improved immunity to wr

1992-03-13

1994-02-22

LaRoche, Eugene R.

Static information storage and retrieval

Floating gate

Particular biasing

365218, 365226, 36518909, G11C 1140, G11C 1606

Patent

active

052894118

ABSTRACT:
An electrically programmable and erasable floating gate memory array device is disclosed. The array has a plurality of column address lines, a plurality of row address lines, and a plurality of common source lines. Each of the memory cells has one terminal connected to one of the column address lines, another one connected to one of the row address lines, and a third connected to one of the common source lines. By appropriate selection circuit, a high voltage source can be connected to either the row address line to effect erasure of charges on the floating gate of the memory cells connected to the selected row address line or to the common source line to selectively program the memory cells connected to the associated common source line. In this manner, write disturbance can be limited.

REFERENCES:
patent: 4601020 (1986-07-01), Arakawa et al.
patent: 4698787 (1987-10-01), Mukherjee et al.
patent: 4949309 (1990-08-01), Rao
patent: 5029130 (1991-07-01), Yeh
patent: 5075890 (1991-12-01), Itoh et al.

Affiliated with

Also associated with

Rating

Floating gate memory array device having improved immunity to wr does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Floating gate memory array device having improved immunity to wr, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Floating gate memory array device having improved immunity to wr will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-177063