Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-12-12
2004-09-21
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185030, C365S185120, C365S185180, C365S185230, C365S185330, C327S537000, C327S538000, C327S540000, C327S541000
Reexamination Certificate
active
06795344
ABSTRACT:
FIELD OF THE INVENTION
The present invention is related to a floating gate memory architecture, and more particularly to a floating gate memory architecture having a current regulator. There are a novel method and circuit to resolve the variation of the regulated voltage to be constant during programming with different programming currents due to the variation of program data.
BACKGROUND OF THE INVENTION
Floating gate memory devices, which are programmed by using hot electron injection and erased by using Fowler Nordheim tunneling, are well-known and described in detail in U.S. Pat. No. 5,029,130.
Please refer to FIG.
1
. When data are written into the memory block
11
, the high voltage that generated by HV source (
22
) is a regulated and precision voltage for a certain range of program current being consumed. However, in order to pass this regulated voltage to the expected source line (
36
a
2
), this high voltage has to pass through the HV decoder (
60
a
) (
FIG. 2
) to reach the designated source line (
36
a
2
). Due to the tight pitch of the memory cell, the transistors (
62
b
) in HV decoder (
60
a
) that have to pass through this regulated high voltage cannot be made as large as we wanted. So that when we program data with “all 0”, the worst program current case (Idp (program current per bit)×8 (For byte programming)) there will be voltage drop between the node V
1
and V
2
due to the size issue of the transistor in the HV decoder (
60
a
). If the program data is “all one” of the best program current case (no Idp at all), V
1
will be almost equal to V
2
. This will cause a problem that the source line voltage (V
2
) during programming will depend on the data being programmed and this problem will made a large variation in programming voltage in source line especially when the program current is large (Ex. program “all 0” in Multi-byte programming operation.)
This situation will come worse when technology goes down to smaller geometry of which can tolerate less margin for program bias variation. The memory cell needs a constant and precise high voltage on the source line for programming otherwise either program disturb or poor programming efficiency will occur.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a current regulator for stabilizing V
2
in a constant voltage by absorbing the extra current of node V
2
according to the different programming data. Therefore the reliability and life cycle of the memory cell will be promoted, and the memory cell design will not be affected when the technology is advanced.
According to the present invention, a floating gate memory architecture having current regulator comprises:
A floating gate memory block having at least a programming voltage node for being programmed a plurality of bits (data) according to the control of a plurality of bit lines;
A high voltage source providing a regulated voltage when the plurality of bits (data) are programmed in;
A high voltage decoder locating between the floating gate memory block and the high voltage source for connecting the voltage to the programming voltage node according to the programming data of the floating gate memory block; and
A current regulator connecting to the programming voltage node, for keeping the programming voltage node in a constant voltage, and making a constant current flowing into said floating gate memory block according to said plurality of bits (data).
In accordance with one aspect of the present invention, the floating gate memory block is a flash memory block. The voltage is provided by the high voltage source when the plurality of bits are programmed into the flash memory block.
In accordance with one aspect of the present invention, the plurality of bits (data) include eight bits.
In accordance with one aspect of the present invention, the high voltage decoder includes several transistors.
In accordance with one aspect of the present invention, the current regulator includes a current adder and a current mirror. The current adder generates a reference program current according to the plurality of bits (data), and the reference program current makes the current mirror absorb an extra current from the programming voltage node. So, the programming voltage node has a constant voltage.
According to the present invention, a current regulator generates a relative load by a plurality of bits (data), and then makes the programming voltage node have a constant voltage. The current regulator comprises:
A current adder for generating the relative load by the plurality of bits (data), and generating a reference program current according to the relative load; and
A current mirror connecting to the current adder for absorbing an extra current from the programming voltage node according to the reference program current, and making the programming voltage node have a constant voltage.
In accordance with one aspect of the present invention, the plurality of bits (data) have eight bits.
In accordance with one aspect of the present invention, the current adder includes a control current source and eight current mapping circuits. These current mapping circuits are parallel and controlled ON/OFF by the eight bits (data).
In accordance with one aspect of the present invention, a current generated by a current mapping circuit is equal to the control current source.
In accordance with one aspect of the present invention, the eight current mapping circuits generate eight currents to form the reference program current.
In accordance with one aspect of the present invention, the control current source is controlled by a bias voltage signal.
In accordance with one aspect of the present invention, the current adder is controlled by an input signal (PROG)(program).
The present invention may best be understood through the following description with reference to the accompanying drawings, in which:
REFERENCES:
patent: 5029130 (1991-07-01), Yeh
patent: 6175521 (2001-01-01), Pascucci et al.
patent: 6178118 (2001-01-01), Lin et al.
patent: 6535425 (2003-03-01), Nawaki et al.
patent: 6603681 (2003-08-01), Micheloni et al.
Bacon & Thomas PLLC
Tran Andrew Q.
Winbond Electronics Corp.
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