1988-06-21
1990-02-27
Edlow, Martin H.
357 16, 357 4, H01L 2978
Patent
active
049050630
ABSTRACT:
A floating gate memory device comprises a channel for conducting carriers from source to drain, a semiconductor heterostructure forming a potential well (floating gate) for confining carriers sufficiently proximate the channel so as to at least partially deplete it, and a graded bandgap injector region between the control gate and the floating gate for controlling the injection of carriers into and out of the potential well. Also described is a three element memory cell, including the memory device and two FETs, which operates from a constant, non-switched supply voltage and two-level control voltages. Arrays of memory devices may also be used to detect light in a variety of applications such as imaging.
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Beltram Fabio
Capasso Federico
Malik Roger J.
Shah Nitin J.
American Telephone and Telegraph Company AT&T Bell Laboratories
Edlow Martin H.
Urbano Michael J.
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