Floating gate interlevel defect monitor and method

Details Floating gate interlevel defect monitor and method Floating gate interlevel defect monitor and method

1996-05-22

1999-03-30

Brown, Glenn W.

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

324763, 324765, 438 17, 438 18, 257 48, G01R 3126

Patent

active

058894101

ABSTRACT:
According to the preferred embodiment, a defect monitor is provided that uses a floating gate structure. The defect monitor includes a common source, a common drain, and a plurality of floating gates interdispersed between the source and drain. Additionally, a conductor covers the plurality of floating gates. By applying a bias to the conductor and measuring the current flowing through the drain and source, the distribution of defects on the semiconductor wafer can be estimated.

REFERENCES:
patent: 3983479 (1976-09-01), Lee et al.
patent: 4115731 (1978-09-01), Axtell, III
patent: 4144493 (1979-03-01), Lee et al.
patent: 4580247 (1986-04-01), Adam
patent: 4595875 (1986-06-01), Chan et al.
patent: 4801869 (1989-01-01), Sprogis
patent: 5087874 (1992-02-01), Robinson
patent: 5155701 (1992-10-01), Komori et al.
patent: 5181205 (1993-01-01), Kertis
patent: 5304925 (1994-04-01), Ebina
patent: 5329228 (1994-07-01), Comeau
patent: 5359291 (1994-10-01), Dommerich, III
patent: 5394101 (1995-02-01), Mitros
patent: 5400344 (1995-03-01), Mori
P. Puri, "Testing MOSFETs for Shorts", IBM Technical Disclosure Bulletin, vol. 15 No. 8, Jan. 1973, pp. 2469-2470.
H. Heimeier, et al., "Interlevel-Short Detector for Semiconductor Arrays", IBM Technical Disclosure Bulletin, vol. 28 No. 5, Oct. 1985, pp. 2008-2009.
A.P. Elias, "Functional Failure Analysis and Diagnostic Model", IBM Technical Disclosure Bulletin, vol. 27 No. 4A, Sep. 1984, pp. 1863-1865.

Affiliated with

Also associated with

Rating

Floating gate interlevel defect monitor and method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Floating gate interlevel defect monitor and method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Floating gate interlevel defect monitor and method will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1217831