Floating gate FPGA cell with select device on drain

Details Floating gate FPGA cell with select device on drain Floating gate FPGA cell with select device on drain

1996-08-27

1998-06-02

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular connection

36518528, 3651851, 257317, 257320, G11C 1604

Patent

active

057611203

ABSTRACT:
The present invention provides for a novel programming operation of a programming portion of an FPGA interconnect cell. The programming portion has an EPROM transistor and a separated select transistor with the gate of the select transistor connected to the control gate of the EPROM transistor. Both transistors have N+ source/drain regions and share a common N+ source/drain region. A first interconnection line is connected to the N+ source/drain region of the EPROM transistor and a second interconnection line connected to the N+ source/drain region of the select transistor. By setting the first interconnection line and the second interconnection line at respective voltages so that majority charge carriers flow from the N+ region of the EPROM transistor through the common N+ region to the N+ source/drain region of the select transistor during a programming operation of a selected FPGA interconnect cell in an array of such cells, drain disturb effects on the unselected cells are avoided.

REFERENCES:
patent: 4783766 (1988-11-01), Samachisa
patent: 5017979 (1991-05-01), Fujii
patent: 5040147 (1991-08-01), Yoshizawa
patent: 5084745 (1992-01-01), Iizuka
patent: 5326999 (1994-07-01), Kim
patent: 5596529 (1997-01-01), Noda

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