Floating gate and fabricating method of the same

Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Between different group iv-vi or ii-vi or iii-v compounds...

Reexamination Certificate

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C257S316000, C257S321000

Reexamination Certificate

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06855966

ABSTRACT:
A floating gate and a fabricating method of the same. A semiconductor substrate is provided. A gate dielectric layer and a conducting layer are sequentially formed on the semiconductor substrate. A patterned hard mask layer having an opening is formed on the conducting layer, wherein a portion of the conducting layer is exposed through the opening. A spacer is formed on the sidewall of the opening. The patterned hard mask layer is removed. A conducting spacer is formed on the sidewall of the spacer. The exposed conducting layer and the exposed gate dielectric layer are sequentially removed.

REFERENCES:
patent: 6468863 (2002-10-01), Hsieh et al.
patent: 6524915 (2003-02-01), Kim et al.
patent: 20040033631 (2004-02-01), Clark et al.

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