Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons
Patent
1993-02-16
1994-06-28
Westin, Edward P.
Electrical transmission or interconnection systems
Nonlinear reactor systems
Parametrons
307465, 307475, H03K 1716
Patent
active
053249968
ABSTRACT:
An input buffer circuit for voltage controlled switch based logic, such as CMOS, which tolerates a floating input voltage without damaging the transistors which form the input buffer circuit. The input buffer circuit protects the input transistors by including an inhibit signal that can be activated to prevent the connection of the system power supply to the system ground when other input signals are floating. The inhibit signal or an independent protection signal further causes the buffer circuit to provide a constant output from the input buffer circuit even when the input voltage floats. Preferred embodiments of the input buffer circuit can be programmed from an internal or external source to cause the output of the buffer circuit to be at an inactive high level or to be at an inactive low level in accordance with whether the input signal being buffered is an inactive high signal or an inactive low signal.
REFERENCES:
patent: 3974403 (1976-08-01), Georgeopoulos
patent: 4585958 (1986-04-01), Chung
patent: 4777389 (1988-10-01), Wu
patent: 4806798 (1989-02-01), Kanauchi
L. Randall Mote, Jr.; AST, Research, Inc. PISA Chip Real Time Clock Schematic; May 9, 1991.
AST Research Inc.
Sanders Andrew
Westin Edward P.
LandOfFree
Floating fault tolerant input buffer circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Floating fault tolerant input buffer circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Floating fault tolerant input buffer circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2379259