Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2007-10-25
2010-11-09
Dinh, Son (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185010, C365S185130
Reexamination Certificate
active
07830722
ABSTRACT:
A plurality of integrated circuit features are provided in the context of an array of memory cells including a plurality of word lines and a plurality of bit lines. Each memory cell includes a floating body or is volatile memory. The aforementioned features may include, among others, an option whereby the foregoing bit lines may be situated below a channel region of corresponding memory cells, etc.
REFERENCES:
patent: 4574365 (1986-03-01), Scheuerlein
patent: 5268870 (1993-12-01), Harari
patent: 5474365 (1995-12-01), Von Linsingen-Heintzmann
patent: 5915167 (1999-06-01), Leedy
patent: 6034882 (2000-03-01), Johnson et al.
patent: 6185122 (2001-02-01), Johnson et al.
patent: 6490218 (2002-12-01), Vyvoda et al.
patent: 6504753 (2003-01-01), Scheuerlein et al.
patent: 6522594 (2003-02-01), Scheuerlein
patent: 6573545 (2003-06-01), Kim et al.
patent: 6618295 (2003-09-01), Scheuerlein
patent: 6631085 (2003-10-01), Kleveland et al.
patent: 6633509 (2003-10-01), Scheuerlein et al.
patent: 6661730 (2003-12-01), Scheuerlein et al.
patent: 6686624 (2004-02-01), Hsu
patent: 6735104 (2004-05-01), Scheuerlein
patent: 6754102 (2004-06-01), Kleveland et al.
patent: 6768685 (2004-07-01), Scheuerlein
patent: 6816410 (2004-11-01), Kleveland et al.
patent: 6822903 (2004-11-01), Scheuerlein et al.
patent: 6856572 (2005-02-01), Scheuerlein et al.
patent: 6859410 (2005-02-01), Scheuerlein et al.
patent: 6920060 (2005-07-01), Chow et al.
patent: 6998677 (2006-02-01), Fastow
patent: 7177191 (2007-02-01), Fasoli et al.
patent: 7221588 (2007-05-01), Fasoli et al.
patent: 7233522 (2007-06-01), Chen et al.
patent: 7317641 (2008-01-01), Scheuerlein
patent: 7319617 (2008-01-01), Park
patent: 7348618 (2008-03-01), Woo et al.
patent: 2002/0022360 (2002-02-01), Kim et al.
patent: 2002/0028541 (2002-03-01), Lee et al.
patent: 2002/0105057 (2002-08-01), Vyvoda et al.
patent: 2003/0081489 (2003-05-01), Scheuerlein et al.
patent: 2004/0007721 (2004-01-01), Forbes et al.
patent: 2004/0100831 (2004-05-01), Knall et al.
patent: 2004/0124415 (2004-07-01), Walker et al.
patent: 2004/0125629 (2004-07-01), Scheuerlein et al.
patent: 2004/0155317 (2004-08-01), Bhattacharyya
patent: 2004/0188714 (2004-09-01), Scheuerlein et al.
patent: 2004/0263238 (2004-12-01), Thorp et al.
patent: 2005/0047240 (2005-03-01), Ikehashi et al.
patent: 2005/0078537 (2005-04-01), So et al.
patent: 2005/0088895 (2005-04-01), Manger et al.
patent: 2006/0285422 (2006-12-01), Scheuerlein
patent: WO 2004/090905 (2001-10-01), None
patent: WO 2004/061861 (2004-07-01), None
patent: WO 2004/061863 (2004-07-01), None
Written Opinion and International Search Report of International Application No. PCT/US2006/023707 dated Feb. 5, 2007.
Notice of Allowance and Fee(s) Due of U.S. Appl. No. 11/157,293 dated Dec. 26, 2007.
Notice of Allowance and Fee(s) Due of U.S. Appl. No. 11/157,293 dated Jan. 27, 2009.
Notice of Allowance and Fee(s) Due of U.S. Appl. No. 11/157,293 dated May 14, 2009.
Office Action of U.S. Appl. No. 11/157,293 dated May 9, 2008.
Office Action of U.S. Appl. No. 11/157,293 dated Jun. 13, 2007.
Nov. 10, 2008 Reply to May 9, 2008 Office Action of U.S. Appl. No. 11/157,293.
Nov. 15, 2007 Supplemental Reply to Jun. 13, 2007 Office Action of U.S. Appl. No. 11/157,293.
Nov. 1, 2007 Reply to Jun. 13, 2007 Office Action of U.S. Appl. No. 11/157,293.
Ohsawa et al., “An I 8.5ns 128 Mb SOI DRAM with a Floating Body Cell”, Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International, vol. Feb. 9, 2005, pp. 458-695.
Ohsawa et al., “Memory Design Using One-Transistor Gain Cell on SOI”, Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International, vol. I, Feb. 3-7, 2002, pp. 152-455.
Ohsaki et al., “A Single Poly EEPROM Cell Structure for Use in Standard CMOS Processes”, IEEE Journal of Solid-State Circuits, vol. 29, No. 3, Mar. 1994.
Ohsawa et al., “Memory Design Using a One-Transistor Gain Cell on SOI”, Nov. 2002, IEEE Journal of Solid-State Circuits, vol. 37, No. 11, pp. 1510-1522.
Tanaka et al., “Scalability Study on a Capacitorless IT-DRAM: From Single-gate PD-SOI to Double-gate FinDRAM”, 2004, IEEE, pp. 37.5.1-37.5.4.
Office Action of U.S. Appl. No. 11/157,293 mailed Oct. 15, 2009.
Jan. 15, 2010 Reply to Office Action of related U.S. Appl. No. 11/157,293 mailed Oct. 15, 2009.
Notice of Allowance of related U.S. Appl. No. 11/157,293 mailed Mar. 8, 2010.
Supplemental Notice of Allowance of related U.S. Appl. No. 11/157,293 dated Mar. 30, 2010.
Dinh Son
Dugan & Dugan PC
Nguyen Nam
SanDisk 3D LLC
LandOfFree
Floating body memory cell system and method of manufacture does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Floating body memory cell system and method of manufacture, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Floating body memory cell system and method of manufacture will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4172772