Floating body cell (FBC) memory device with a sense...

Details Floating body cell (FBC) memory device with a sense... Floating body cell (FBC) memory device with a sense...

2007-01-23

2008-10-21

Tran, Andrew Q (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185210, C365S185250, C365S185230, C365S185260

Reexamination Certificate

active

07440329

ABSTRACT:
This disclosure concerns a semiconductor memory including memory cells; a first dummy cell and a second dummy cell generating a reference potential and storing first data and second data of mutually opposite polarities, respectively; word lines; a first and a second dummy word lines connected to gates of the first and the second dummy cells; a pair of bit lines; and a sense amplifier provided for the pair of bit lines, the sense amplifier detecting the first data using the second data as a reference or detecting the second data using the first data as a reference in a refresh operation of the first and the second dummy cells.

REFERENCES:
patent: 7145811 (2006-12-01), Ohsawa
patent: 2007/0195626 (2007-08-01), Kim et al.
patent: 2008/0049529 (2008-02-01), Ohsawa
patent: 0678919 (1995-10-01), None
patent: 2007-207358 (2007-08-01), None
Takashi Ohsawa, et al., “An 18.5ns 128Mb SOI DRAM with a Floating Body Cell”, ISSCC 2005, Digest of Technical Papers, Session 25, Dynamic Memory, 25.1, Feb. 2005, 3 Pages.

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