Float register spill cache method, system, and computer program

Details Float register spill cache method, system, and computer program Float register spill cache method, system, and computer program

1996-07-01

1999-05-04

Trammell, James P.

395701, 395562, 395563, G06F 1208, G06F 944

Patent

active

059013168

ABSTRACT:
A float register spill cache method for improving the efficiency of usage of floating point single precision registers computer using a microprocessor conforming to the SPARC-V9 architecture specification. Values are temporarily stored in a plurality of double precision registers which are utilized as a float spill cache having a plurality of float spill slots. Values are generally shifted from one of the single precision registers to a second single precision register which is used as a spill pad, and then from the spill pad to a selected one of the float spill slots.

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