Flipping algorithm to architectures of hardware realization...

Details Flipping algorithm to architectures of hardware realization... Flipping algorithm to architectures of hardware realization...

2006-07-11

2006-07-11

Ngo, Chuong D. (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

07076515

ABSTRACT:
A flipping algorithm for the hardware realization of Lifting-based DWT, relates a flipping algorithm and hardware architecture for the hardware realization of Lifting-based DWT, by using lifting architecture as starting point, by multiplying the edge of the cutset which is through the multiplier and the basic computing unit by the reciprocal of multiplier coefficient in order to cut off the accumulation effect of timing delay. And separating the computing node of said basic computing units into 2 adders then applying flipping architecture to shorten the critical path, therefore not only can keep the merits of Lifting Scheme in hardware requirement but also can shorten the critical path to achieve the optimized hardware architecture.

REFERENCES:
patent: 6567081 (2003-05-01), Li et al.
patent: 6757343 (2004-06-01), Ortega et al.
patent: 6795504 (2004-09-01), Xu et al.
patent: 6904177 (2005-06-01), Nakayama

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