Flip-flop with false triggering prevention circuit

Details Flip-flop with false triggering prevention circuit Flip-flop with false triggering prevention circuit

1976-07-14

1977-09-13

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307246, 307234, H03K 3286

Patent

active

040485218

ABSTRACT:
A set-reset flip-flop is taught utilizing NAND gate logic elements and an internally connected resistor-capacitor circuit. The time constant of the resistor-capacitor network is such that valid triggering pulses for the input terminal of the flip-flop will not be propagated through the flip-flop to change the output state thereof unless the pulses are of a minimum duration. The duration of such pulses are chosen to be significantly larger than the duration of expected random noise which may appear on the input terminal of the flip-flop. Such being the case, noise signals are not propagated through the flip-flop to change the state thereof. A discharge network is provided for the capacitor to quickly discharge the capacitor at the termination of each input pulse, whether noise or triggering, so that an accummulaton of noise pulses will not cause a shift in the output of the flip-flop.

REFERENCES:
patent: 3225221 (1965-12-01), Scott
patent: 3327134 (1967-06-01), Keane
patent: 3349255 (1967-10-01), McAvoy

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