Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit
Reexamination Certificate
2001-09-10
2002-12-10
Ton, My-Trang Nu (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Particular stable state circuit
C327S212000
Reexamination Certificate
active
06492855
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to flip flops and, more particularly, to a flip flop which has complementary, symmetric, minimal timing skew outputs.
2. Description of the Related Art
A flip flop is a device which latches the logic state of a data input signal when a predetermined edge of a clock input signal is detected. As a result, a flip flop generates a flop data output signal whose logic state matches the logic state of the data input signal when the predetermined edge of the clock input signal is detected. Additionally, flip flops typically contain a second data output signal whose logic state is the complement (logical inverse) of the first data output signal.
If a flip flop has true/complementary data outputs which are exact mirror images of each other in the time domain, these outputs are said to be complementary and symmetric. Therefore, the rise time of the true data output signal and the fall time of the complementary data output signal must be equal, and the fall time of the true data output signal and the rise time of the complementary data output signal must also be equal. As a result, the flop true/complementary data outputs must change state at exactly the same time, such that both of them will reach the power supply mid-point voltage at exactly the same time.
FIG. 1
shows a timing diagram which illustrates the operation of a flip flop that has complementary, symmetric outputs. As shown in
FIG. 1
, the flip flop generates a data output signal Q and a complementary data output signal QZ. In addition, the Q and QZ data outputs have equal rise and fall times (equal to two time units). Furthermore, the Q and QZ data outputs change state at exactly the same time, so that they reach the power supply mid-point voltage VDD/2 at exactly the same time.
Many applications require the use of flip flops which have complementary, symmetric outputs. High accuracy digital-to-analog converters (DACs) are an important example. High accuracy DACs are used in a wide variety of applications, including telecommunications, control systems and filters for digital signal processors.
FIG. 2
shows a schematic diagram which illustrates a conventional digital-to-analog interface
200
for one bit of a high-accuracy differential DAC. As shown in
FIG. 2
, interface
200
includes a flip flop FF
1
which has a data input
210
that receives a data signal DATA, and a clock input
212
that receives a clock signal CLK. Flip flop FF
1
also has complementary, symmetric outputs which include a data output
214
that generates a flop signal Q, and a complementary data output
216
that generates a complementary flop signal QZ.
Referring to
FIG. 2
, interface
200
also includes a pair of p-channel load transistors M
1
and M
2
, a pair of differential input transistors M
3
and M
4
, and a current source I. P-channel transistors Ml and M
2
both have sources connected to a power supply voltage VDD. In addition, transistor M
1
has a gate and a drain connected to a first output node N
1
, while transistor M
2
has a gate and a drain connected to a second output node N
2
.
N-channel transistors M
3
and M
4
both have sources connected to current source I which, in turn, is connected to ground. In addition, transistor M
3
has a gate connected to data output
214
and a drain connected to first output node N
1
, while transistor M
4
has a gate connected to data output
216
and a drain connected to second output node N
2
. A differential output is taken across output nodes N
1
and N
2
.
In order to maintain high DAC accuracy, the complementary flop output signals Q and QZ must be mirror images of each other in the time domain. In other words, their rise and fall times must be equal to each other, and they must change state at exactly the same time.
When these conditions are met, the rising and falling waveforms of Q and QZ will cross each other at exactly one half of the power supply voltage (VDD/2), thereby producing an undistorted differential output waveform at nodes N
1
and N
2
.
FIG. 3
shows the schematic diagram of a prior art flip flop
300
. Referring to
FIG. 3
, flop
300
has a clock inverter U
1
, a master latch
310
, and a slave latch
312
. Clock inverter U
1
has an input connected to an external clock input
314
to receive a clock signal CLK, and an output which generates an inverted clock signal CPZ.
Master latch
310
includes a first transmission gate
316
and a second transmission gate
318
. First transmission gate
316
includes an n-channel transistor M
1
which has a drain connected to an external data input
320
to receive a data signal D, a source, and a gate connected to the output of clock inverter U
1
to receive the inverted clock signal CPZ.
First transmission gate
316
also includes a p-channel transistor M
2
which has a source connected to external data input
320
to receive the data signal D, a drain connected to the source of transistor M
1
, and a gate connected to external clock input
314
to receive the clock signal CLK.
Second transmission gate
318
includes an n-channel transistor M
3
which has a drain, a source connected to the source of transistor M
1
, and a gate connected to external clock input
314
to receive the clock signal CLK. Second transmission gate
318
also includes a p-channel transistor M
4
which has a source connected to the drain of transistor M
3
, a drain connected to the source of transistor M
3
, and a gate connected to the output of clock inverter U
1
to receive the inverted clock signal CPZ.
In addition to first and second transmission gates
316
and
318
, master latch
310
also includes an inverter U
2
which has an input connected to the source of transistor M
1
, and an output which generates a latched signal QM. Master latch
310
additionally includes an inverter U
3
which has an input connected to the output of inverter U
2
, and an output which is connected to the drain of transistor M
3
.
Slave latch
312
includes a third transmission gate
324
and a fourth transmission gate
326
. Third transmission gate
324
includes an n-channel transistor M
5
and a p-channel transistor M
6
. Transistor M
5
has a drain connected to the output of inverter U
2
to receive the latched signal QM, a source, and a gate connected to external clock input
314
to receive the clock signal CLK. Transistor M
6
has a source connected to the output of inverter U
2
to receive the latched signal QM, a drain connected to the source of transistor M
5
, and a gate connected to the output of clock inverter U
1
to receive the inverted clock signal CPZ.
Fourth transmission gate
326
includes an n-channel transistor M
7
which has a drain, a source connected to the source of transistor M
5
, and a gate connected to the output of clock inverter U
1
to receive the inverted clock signal CPZ. Fourth transmission gate
326
also includes a p-channel transistor M
8
which has a source connected to the drain of transistor M
7
, a drain connected to the source of transistor M
7
, and a gate connected to external clock input
314
to receive the clock signal CLK.
In addition to transmission gates
324
and
326
, slave latch
312
also includes an inverter U
4
and an inverter U
5
. Inverter U
4
has an input connected to the source of transistor M
5
and an output, while inverter U
5
has an input connected to the output of inverter U
4
, and an output which generates the inverted flop signal QZ.
Slave latch
312
also includes an inverter U
6
and an inverter U
7
. Inverter U
6
has an input connected to the output of inverter U
4
, and an output connected to the drain of transistor M
7
. Inverter U
7
has an input connected to the output of inverter U
6
, and an output which generates the flop data signal Q.
In operation, flop
300
attempts to generate complementary, symmetric outputs at Q and QZ by equalizing the propagation delay in two output signal paths. The first output signal path is from the input of inverter U
4
to the output of inverter U
5
, ending with the inverted f
National Semiconductor Corporation
Nu Ton My-Trang
Pickering Mark C.
LandOfFree
Flip flop which has complementary, symmetric, minimal timing... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Flip flop which has complementary, symmetric, minimal timing..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Flip flop which has complementary, symmetric, minimal timing... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2976594