Flip-flop programmer using cascaded logic arrays

Details Flip-flop programmer using cascaded logic arrays Flip-flop programmer using cascaded logic arrays

1982-12-10

1985-06-25

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307272R, 307445, 364716, 377 54, H03K 19173, H03K 3027

Patent

active

045256411

ABSTRACT:
Cascaded programmable logic arrays are used to program any type of flip-flop. The latch itself can be embedded in the array when using cascaded PLA's. The arrays can be cascaded to provide logic functions using less total area than a single array embodying the same function.

REFERENCES:
patent: 3566153 (1971-02-01), Spencer, Jr.
patent: 3993919 (1976-11-01), Cox et al.
patent: 4034356 (1977-07-01), Howley et al.
patent: 4267463 (1981-05-01), Mayumi
Long, "Input Bus Switching for PLA"; IBM Tech. Discl. Bull.; vol. 20, No. 3, p. 1062; 8/1977.
O'Hara, Jr., "PLA Multifunction Latches"; IBM Tech. Discl. Bull.; vol. 20, No. 12, pp. 5205-5208; 5/1978.
Greenspan, "Multiple Partioned Programmable Logic Array"; IBM Tech. Discl. Bull.; vol. 19, No. 5; pp. 1780-1781; 10/1976.
Mitchell, "Programmable Logic Arrays"; Electronic Design, 15, 7/19/76; pp. 98-101.
IBM Technical Disclosure Bulletin, "Programmable Flip-Flop", J. E. Gersbach, vol. 18, No. 5, Oct. 1975.
IBM Technical Disclosure Bulletin, "PLA Having OR-Array Bit Partitioning", L. D. Whitley, vol. 24, No. 6, Nov. 1981.

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