Flip-flop having reset preferential function

Details Flip-flop having reset preferential function Flip-flop having reset preferential function

1977-11-21

1979-12-18

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307205, 307232, 307247R, 307291, H03K 3286, H03K 3353, H03K 520, H03D 1300

Patent

active

041796284

ABSTRACT:
A flip-flop having a reset preferential function, comprising a set input terminal, a reset input terminal, a clock signal source operatively coupled through a field effect transistor to the set input terminal, a capacitance formed at the gate electrode of the field effect transistor, a charge control transistor controllable responsive to the clock signal for precharging the capacitance prior to the clock signal, a discharge control transistor controllable responsive to the reset signal for discharging the capacitance, whereby the capacitance is precharged prior to the clock signal and is discharged responsive to the reset signal, the field effect transistor being rendered conductive as a function of the electric charge of the capacitance, the clock signal source being operatively coupled to the set input terminal as a function of the conduction state of the field effect transistor, whereby the flip-flop is set responsive to the leading edge of the clock signal and is reset responsive to the reset signal in preference to the clock signal.

REFERENCES:
patent: 3710140 (1973-01-01), Volmerange
patent: 3812384 (1974-05-01), Skorup
patent: 3892985 (1975-07-01), Kawagoe
patent: 3976949 (1976-08-01), Hepworth
patent: 3983496 (1976-09-01), Bedford et al.
patent: 3986128 (1976-10-01), Eriksson et al.
patent: 4011465 (1977-03-01), Alvarez, Jr.
patent: 4024416 (1977-05-01), Fujita et al.
patent: 4105947 (1978-08-01), Crowley
patent: 4122405 (1978-10-01), Tietz et al.

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